Measurement Computing USB-3102 - Manual (Page 23)

USB-3102 User's Guide Specifications
23
Synchronous DAC Load
Table 8. SYNCLD I/O specifications
Parameter Conditions Specification
Pin name SYNCLD (terminal block pin 49)
Power on and reset state Input
Pin type Bidirectional
Termination Internal 100K ohms pull-down
Software selectable direction Output Outputs internal D/A LOAD signal.
Input Receives D/A LOAD signal from external source.
Input clock rate 100 Hz max
Clock pulse width Input 1 µs min
Output 5 µs min
Input leakage current ±1.0 µA typ.
Input high voltage 4.0 V min, 5.5 V absolute max
Input low voltage 1.0 V max, –0.5 V absolute min
Output high voltage (Note 9) IOH = –2.5 mA 3.3 V min
No load 3.8 V min
Output low voltage (Note 10) IOL = 2.5 mA 1.1 V max
No load 0.6 V max
Note 9: SYNCLD is a Schmitt trigger input and is over-current protected with a 200 Ohm series resistor.
Note 10: When SYNCLD is in input mode, the analog outputs may either be updated immediately or when
a positive edge is seen on the SYNCLD pin (this is under software control.) However, the pin
must be at a low logic level in order for the DAC outputs to be updated immediately. If an
external source is pulling the pin high, no update will occur.
Counter
Table 9. CTR I/O specifications
Parameter Conditions Specification
Pin name CTR
Number of channels 1
Resolution 32-bits
Counter type Event counter
Input type TTL, rising edge triggered
Counter read/writes rates
(software paced) Counter read System dependent, 33 to 1000 reads per second.
Counter write System dependent, 33 to 1000 reads per second.
Schmidt trigger hysteresis 20 mV to 100 mV
Input leakage current ±1.0 µA typ.
Input frequency 1 MHz max.
High pulse width 500 nS min.
Low pulse width 500 ns min.
Input high voltage 4.0 V min, 5.5 V absolute max
Input low voltage 1.0 V max, –0.5 V absolute min
Memory
Table 10. Memory specifications