Measurement Computing PCM-DAC08 - Manual (Page 19)

WRITE: D/A Data can be written to this address and to Base + 1 to form a 12 bit D/A
data word. All 8 DAC’s are updated using this register. The DAC being updated is
set via the Select bits (S3 to S0) in the Base +2 register.
READ: Starts a D/A conversion, updates the output of the selected DAC.
D/A0 D/A1 D/A2 D/A3 D/A4 D/A5 D/A6 D/A7
0 1 2 3 4 5 6 7
BASE + 1 - DAC Value MSB (4 bits)
WRITE: Send DAC data.
READ: Clear Interrupt Request bit at Base +4 bit D#3
D/A8 D/A9 D/A10 D/A11 D/A12 X X X
0 1 2 3 4 5 6 7
BASE + 2 - DAC Select Register
WRITE: Set the DAC to update
READ: Read back current DAC updating
D/A0 D/A1 D/A2 D/A3 D/A4 D/A5 D/A6 D/A7
0 1 2 3 4 5 6 7
Update all 8 DACs simultaneously. No write function. X X X 1
Latch new D/A value for DAC7 Update DAC 6 & 7 1 1 1 0
Latch new D/A value for DAC6 Update DAC 6 & 7 0 1 1 0
Latch new D/A value for DAC5 Update DAC 4 & 5 1 0 1 0
Latch new D/A value for DAC4 Update DAC 4 & 5 0 0 1 0
Latch new D/A value for DAC3 Update DAC 2 & 3 1 1 0 0
Latch new D/A value for DAC2 Update DAC 2 & 3 0 1 0 0
Latch new D/A value for DAC1 Update DAC 0 & 1 1 0 0 0
Latch new D/A value for DAC0 Update DAC 0 & 1 0 0 0 0
FUNCTION WR FUNCTION RD S0 S1 S2 S3
Note that DACs are always updated in pairs. For example, if you latch new data to
DAC1, then update the DAC0 and DAC1 pair, DAC1 updates with the new value and
DAC0 updates with the same value as before since the latch (data for output) has not
changed.
CLR: Setting the CLR bit to 1 resets all 8 DACs output to 0V. Default and normal
operation is CLR=0, which has no effect on the DAC outputs.
BASE + 3 - Digital I/O (8 bits)
WRITE: Updates output of DIO bits set for output.
READ: Reads current status of DIO bits for input. Reads back output state of DIO
bits set for output.
16