Sundance PARS User Manual

Page 51

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Revision 11-wip-7

Page 51 of 70

Sundance Digital Signal Processing, Inc.

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.

email:

[email protected]

Tel: +1 (775) 827-3103

www.sundancedsp.com

Type

ClockFreq

DSP Type Fields

Optimization Type

FPGA Type Fields

FPGAType

Wire Declarations

Name

StartProcessorName

StartProcessorPort

EndProcessorName

EndProcessorPort

Command

Footer

4.8.3.

Model Based Input (.mdl file)

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