Sundance SMT351T User Manual
Page 13
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SMT351T User Guide
Page 13 of 37
Last Edited: 04/09/2009 11:26:00
The Reset control is operated by the CPLD line FPGAResetn.
The following diagram shows the CPLD states after Reset.
Figure 2: CPLD state machine
If you implement comport 3 in the FPGA you have to use
Fpgaresetn generated by the CPLD, as the comport is shared
between the two.
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