Sundance SMT370v2 - Manual (Page 38)

Version 2.0 Page 38 of 46 SMT370v2/v3 User Manual
A Decimation Factor of 0 (default value) does not have any effect on the data flow.
When it is set to 1, one sample out of two is trimmed out. When it is set to 2, one out
of three is trimmed out and so on. The maximum value is 31.
The External Trigger signal is routed from connector J15 to the FPGA. Two clamping
diodes avoid too high amplitude signals to damage the FPGA.
Channel A selection:
- “000”=Channel disabled,
- “001”=16-bit counter on clock ADCA,
- “010”=Channel A two’s complement encoding, i.e. samples go straight through
as ADCs output samples in two’s complement 14-bit format. 14-bit samples
coming from the ADC are extended to 16-bit on SHBA – Bit13 is copied onto
Bits14 and 15.
- “011”=Channel A binary encoding. Binary conversion consists in inverting the
MSB of each sample. This operation introduces a DC offset of half the full
scale, which can be removed by subtracting 8192 (decimal) of each sample.
Channel B selection:
- “000”=Channel Disabled,
- “001”=16-bit counter on clock ADCB,
- “010”=Channel B two’s complement encoding, i.e. samples go straight through
as ADCs output samples in two’s complement 14-bit format. 14-bit samples
coming from the ADC are extended to 16-bit on SHBA – Bit13 is copied onto
Bits14 and 15.
- “011”=Channel B binary encoding. Binary conversion consists in inverting the
MSB of each sample. This operation introduces a DC offset of half the full
scale, which can be removed by subtracting 8192 (decimal) of each sample.