Sundance SMT398 - Manual (Page 3)

Version 1.2.0 Page 3 of 52 SMT398 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of Figures.......................................................................................................... 6
Table of Tables........................................................................................................... 6
Physical Properties ..................................................................................................... 8
Introduction................................................................................................................. 9
Related Documents ................................................................................................ 9
Block Diagram ............................................................................................................ 9
Mechanical Interface: TIM Standard......................................................................... 10
SMT398 Support ...................................................................................................... 10
SMT398 Installation .................................................................................................. 10
SMT398 Alone ...................................................................................................... 10
SMT398 + DSP TIM.............................................................................................. 12
FPGA Configuration ................................................................................................. 13
Electrical Interface .................................................................................................... 13
The service CPLD ................................................................................................. 13
CPLD Functions ................................................................................................ 14
Virtex II Bitstream Format.................................................................................. 19
Bitstream Re-formatting..................................................................................... 20
CPLD code versions.......................................................................................... 20
FPGA .................................................................................................................... 20
FPGA in system programming .......................................................................... 22
JTAG/Boundary Scan........................................................................................ 23
Configuring with MultiLINX ................................................................................ 24
FPGA Readback and Partial reconfiguration..................................................... 24
Memory ................................................................................................................. 25
Pipelined ZBTRAM ............................................................................................ 25
Constraints File Signal Names .......................................................................... 27
QDR (Quad Data Rate) ..................................................................................... 27
Constraints File Signal Names .......................................................................... 29
Comports .............................................................................................................. 29