Fpga video control registers – Sundance SMT319 User Manual
Page 20

Version 1.0.7
Page 20 of 45
SMT319 User Manual
FPGA Video Control Registers
Function Size
(bytes)
Address
Colour space converter control
Optional
1k -
Threshold
256 byte LUT
256 -
Video input FIFO
16 bit wide YC FIFO
Readable via or EMIFA
1024 0x90050000
Video input Status Register
4
0x90058000
Video input pixels per frame
Max pixels per frame is < 500k
4 -
Video Input Flag Register
Sets the point at which an interrupt is
generated
4 0x90054000
Interrupt enable
Video input/output interrupt enable
1 0x900E4000
0x900EC000
0x900F4000
0x900FC000
I2C Control
16
-
Video output FIFO
16 bit wide YC FIFO
Writeable via EMIFA
1024 0x90070000
Video Output Status Register 4
0x90078000
Video output mode control
This determines the number of pixels per line,
and lines per frame.
1 0x90078800
Video Output Flag Register
Sets the point at which an interrupt is
generated
4 0x9007C000