Document Outline

• S1C33210 Technical Manual
  • NOTICE
  • Preface
  • New configuration of product number
  • Table of Contents
    • S1C33210 PRODUCT PART Table of Contents
    • S1C33210 FUNCTION PART Table of Contents
  • S1C33210 PRODUCT PART
    • 1 Outline
      • 1.1 Features
      • 1.2 Block Diagram
      • 1.3 Pin Description
        • 1.3.1 Pin Layout Diagram (plastic package)
        • 1.3.2 Pin Functions
    • 2 Power Supply
      • 2.1 Power Supply Pins
      • 2.2 Operating Voltage (VDD, VSS)
      • 2.3 Power Supply for Analog Circuits (AVDD)
    • 3 Internal Memory
      • 3.1 ROM and Boot Address
      • 3.2 RAM
    • 4 Peripheral Circuits
      • 4.1 List of Peripheral Circuits
      • 4.2 I/O Memory Map
    • 5 Power-Down Control
    • 6 Basic External Wiring Diagram
    • 7 Precautions on Mounting
    • 8 Electrical Characteristics
      • 8.1 Absolute Maximum Rating
      • 8.2 Recommended Operating Conditions
      • 8.3 DC Characteristics
      • 8.4 Current Consumption
      • 8.5 A/D Converter Characteristics
      • 8.6 AC Characteristics
        • 8.6.1 Symbol Description
        • 8.6.2 AC Characteristics Measurement Condition
        • 8.6.3 C33 Block AC Characteristic Tables
        • 8.6.4 C33 Block AC Characteristic Timing Charts
      • 8.7 Oscillation Characteristics
      • 8.8 PLL Characteristics
    • 9 Package
      • 9.1 Plastic Package
    • 10 Pad Layout
      • 10.1 Pad Layout Diagram
      • 10.2 Pad Coordinate
    • Appendix A <Reference> External Device Interface Timings
      • A.1 DRAM (70ns)
      • A.2 DRAM (60ns)
      • A.3 ROM and Burst ROM
      • A.4 SRAM (55ns)
      • A.5 SRAM (70ns)
      • A.6 8255A
    • Appendix B Pin Characteristics
  • S1C33210 FUNCTION PART
    • I OUTLINE
      • I-1 INTRODUCTION
      • I-2 BLOCK DIAGRAM
      • I-3 LIST OF PINS
        • List of External I/O Pins
    • II CORE BLOCK
      • II-1 INTRODUCTION
      • II-2 CPU AND OPERATING MODE
        • CPU
        • Standby Mode
          • HALT Mode
          • SLEEP Mode
          • Notes on Standby Mode
        • Test Mode
        • Debug Mode
        • Trap Table
      • II-3 INITIAL RESET
        • Pins for Initial Reset
        • Cold Start and Hot Start
        • Power-on Reset
        • Reset Pulse
        • Boot Address
        • Notes Related to Initial Reset
      • II-4 BCU (Bus Control Unit)
        • Pin Assignment for External System Interface
          • I/O Pin List
          • Combination of System Bus Control Signals
        • Memory Area
          • Memory Map
          • External Memory Map and Chip Enable
          • Using Internal Memory on External Memory Area
          • Exclusive Signals for Areas
          • Area 10
          • Area 3
        • Setting External Bus Conditions
          • Setting Device Type and Size
          • Setting SRAM Timing Conditions
          • Setting Timing Conditions of Burst ROM
        • Bus Operation
          • Data Arrangement in Memory
          • Bus Operation of External Memory
        • Bus Clock
          • Bus Speed Mode
          • Bus Clock Output
        • Bus Cycles in External System Interface
          • SRAM Read Cycles
          • Bus Timing
          • SRAM Write Cycles
          • Burst ROM Read Cycles
        • DRAM Direct Interface
          • Outline of DRAM Interface
          • DRAM Setting Conditions
          • DRAM Read/Write Cycles
          • DRAM Refresh Cycles
        • Releasing External Bus
        • Power-down Control by External Device
        • I/O Memory of BCU
        • Programming Notes
      • II-5 ITC (Interrupt Controller)
        • Outline of Interrupt Functions
          • Maskable Interrupts
          • Interrupt Factors and Intelligent DMA
          • Nonmaskable Interrupt (NMI)
          • Interrupt Processing by the CPU
          • Clearing Standby Mode by Interrupts
        • Trap Table
        • Control of Maskable Interrupts
          • Structure of the Interrupt Controller
          • Processor Status Register (PSR)
          • Interrupt Factor Flag and Interrupt Enable Register
          • Interrupt Priority Register and Interrupt Levels
        • IDMA Invocation
        • HSDMA Invocation
        • I/O Memory of Interrupt Controller
        • Programming Notes
      • II-6 CLG (Clock Generator)
        • Configuration of Clock Generator
        • I/O Pins of Clock Generator
        • High-Speed (OSC3) Oscillation Circuit
        • PLL
        • Controlling Oscillation
        • Setting and Switching Over the CPU Operating Clock
        • Power-Control Register Protection Flag
        • Operation in Standby Mode
        • I/O Memory of Clock Generator
        • Programming Notes
      • II-7 DBG (Debug Unit)
        • Debug Circuit
        • I/O Pins of Debug Circuit
    • III PERIPHERAL BLOCK
      • III-1 INTRODUCTION
      • III-2 PRESCALER
        • Configuration of Prescaler
        • Source Clock
        • Selecting Division Ratio and Output Control for Prescaler
        • Source Clock Output to 8-Bit Programmable Timer
        • I/O Memory of Prescaler
        • Programming Notes
      • III-3 8-BIT PROGRAMMABLE TIMERS
        • Configuration of 8-Bit Programmable Timer
        • Output Pins of 8-Bit Programmable Timers
        • Uses of 8-Bit Programmable Timers
        • Control and Operation of 8-Bit Programmable Timer
        • Control of Clock Output
        • 8-Bit Programmable Timer Interrupts and DMA
        • I/O Memory of 8-Bit Programmable Timers
        • Programming Notes
      • III-4 16-BIT PROGRAMMABLE TIMERS
        • Configuration of 16-Bit Programmable Timer
        • I/O Pins of 16-Bit Programmable Timers
        • Uses of 16-Bit Programmable Timers
        • Control and Operation of 16-Bit Programmable Timer
        • Controlling Clock Output
        • 16-Bit Programmable Timer Interrupts and DMA
        • I/O Memory of 16-Bit Programmable Timers
        • Programming Notes
      • III-5 WATCHDOG TIMER
        • Configuration of Watchdog Timer
        • Control of Watchdog Timer
        • Operation in Standby Modes
        • I/O Memory of Watchdog Timer
        • Programming Notes
      • III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT
        • Configuration of Low-Speed (OSC1) Oscillation Circuit
        • I/O Pins of Low-Speed (OSC1) Oscillation Circuit
        • Oscillator Types
        • Controlling Oscillation
        • Switching Over the CPU Operating Clock
        • Power-Control Register Protection Flag
        • Operation in Standby Mode
        • OSC1 Clock Output to External Devices
        • I/O Memory of Clock Generator
        • Programming Notes
      • III-7 CLOCK TIMER
        • Configuration of Clock Timer
        • Control and Operation of the Clock Timer
        • Interrupt Function
        • Examples of Use of Clock Timer
        • I/O Memory of Clock Timer
        • Programming Notes
      • III-8 SERIAL INTERFACE
        • Configuration of Serial Interfaces
          • Features of Serial Interfaces
        • I/O Pins of Serial Interface
          • Setting Transfer Mode
        • Clock-Synchronized Interface
          • Outline of Clock-Synchronized Interface
          • Setting Clock-Synchronized Interface
          • Control and Operation of Clock-Synchronized Transfer
        • Asynchronous Interface
          • Outline of Asynchronous Interface
          • Setting Asynchronous Interface
          • Control and Operation of Asynchronous Transfer
        • IrDA Interface
          • Outline of IrDA Interface
          • Setting IrDA Interface
          • Control and Operation of IrDA Interface
        • Serial Interface Interrupts and DMA
        • I/O Memory of Serial Interface
        • Programming Notes
      • III-9 INPUT/OUTPUT PORTS
        • Input Ports (K Ports)
          • Structure of Input Port
          • Input-Port Pins
          • Notes on Use
          • I/O Memory of Input Ports
        • I/O Ports (P Ports)
          • Structure of I/O Port
          • I/O Port Pins
          • I/O Control Register and I/O Modes
          • I/O Memory of I/O Ports
        • Input Interrupt
          • Port Input Interrupt
          • Key Input Interrupt
          • Control Registers of the Interrupt Controller
          • I/O Memory for Input Interrupts
          • Programming Notes
      • III-10 Monitored Mobile Access Interfaces
        • Configuration of Mobile Access Interfaces
          • I/O Pins for Mobile Access Interfaces
          • Basic Settings for Mobile Access Interfaces
        • UART Communications Mode
          • Overview
        • PDC Communications Mode
          • Overview
          • PDC Communications Control and Operation
        • PHS Communications Mode
          • PHS Communications Control and Operation
        • HDLC Communications Mode
          • Overview
          • HDLC Communications Control and Operation
        • Mobile Access Interface Interrupts
          • Overview
          • Mobile Access Interface Interrupt Outputs
        • I/O Memory for Mobile Access Interfaces
        • Important Notes on Debugging
    • IV ANALOG BLOCK
      • IV-1 INTRODUCTION
      • IV-2 A/D CONVERTER
        • Features and Structure of A/D Converter
        • I/O Pins of A/D Converter
        • Setting A/D Converter
        • Control and Operation of A/D Conversion
        • A/D Converter Interrupt and DMA
        • I/O Memory of A/D Converter
        • Programming Notes
    • V DMA BLOCK
      • V-1 INTRODUCTION
      • V-2 HSDMA (High-Speed DMA)
        • Functional Outline of HSDMA
        • I/O Pins of HSDMA
        • Programming Control Information
          • Setting the Registers in Dual-Address Mode
          • Setting the Registers in Single-Address Mode
        • Enabling/Disabling DMA Transfer
        • Trigger Factor
        • Operation of HSDMA
          • Operation in Dual-Address Mode
          • Operation in Single-Address Mode
          • Timing Chart
        • Interrupt Function of HSDMA
        • I/O Memory of HSDMA
        • Programming Notes
      • V-3 IDMA (Intelligent DMA)
        • Functional Outline of IDMA
        • Programming Control Information
        • IDMA Invocation
        • Operation of IDMA
        • Linking
        • Interrupt Function of Intelligent DMA
        • I/O Memory of Intelligent DMA
        • Programming Notes
    • Appendix I/O MAP
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