Document Outline

• 1. Introduction
  • 1.1 Purpose
  • 1.2 Industry Standard
    • 1.2.1 Intelligent Platform Management Interface (IPMI)
    • 1.2.2 Baseboard Management Controller (BMC)
      • 1.2.2.1 System Event Log (SEL)
    • 1.2.3 Intel® Intelligent Power Node Manager Version 2.0
• 2. Basic Decoding of a SEL Record
  • 2.1 Default Values in the SEL Records
  • 2.2 Notes on SEL Logs and Collecting SEL Information
    • 2.2.1 Examples of Decoding BIOS Timestamp Events
      • 2.2.1.1 BIOS POST Timestamp Events
      • 2.2.1.2 BIOS SMI Handler Timestamp Events
    • 2.2.2 Example of Decoding a PCI Express* Correctable Error Events
    • 2.2.3 Example of Decoding a Power Supply Predictive Failure Event
• 3. Sensor Cross Reference List
  • 3.1 BMC owned Sensors (GID = 0020h)
  • 3.2 BIOS POST owned Sensors (GID = 0001h)
  • 3.3 BIOS SMI Handler owned Sensors (GID = 0033h)
  • 3.4 Node Manager / ME Firmware owned Sensors (GID = 002Ch or 602Ch)
  • 3.5 Microsoft* OS owned Events (GID = 0041)
  • 3.6 Linux* Kernel Panic Events (GID = 0021)
• 4. Power Subsystems
  • 4.1 Threshold-based Voltage Sensors
  • 4.2 Voltage Regulator Watchdog Timer Sensor
    • 4.2.1 Voltage Regulator Watchdog Timer Sensor – Next Steps
  • 4.3 Power Unit
    • 4.3.1 Power Unit Status Sensor
    • 4.3.2 Power Unit Redundancy Sensor
    • 4.3.3 Node Auto Shutdown Sensor
      • 4.3.3.1 Node Auto Shutdown Sensor – Next Steps
  • 4.4 Power Supply
    • 4.4.1 Power Supply Status Sensors
    • 4.4.2 Power Supply Power In Sensors
    • 4.4.3 Power Supply Current Out % Sensors
    • 4.4.4 Power Supply Temperature Sensors
    • 4.4.5 Power Supply Fan Tachometer Sensors
      • 4.4.5.1 Power Supply Fan Tachometer Sensors – Next Steps
• 5. Cooling Subsystem
  • 5.1 Fan Sensors
    • 5.1.1 Fan Tachometer Sensors
    • 5.1.2 Fan Presence and Redundancy Sensors
  • 5.2 Temperature Sensors
    • 5.2.1 Threshold-based Temperature Sensors
    • 5.2.2 Thermal Margin Sensors
    • 5.2.3 Processor Thermal Control Sensors
      • 5.2.3.1 Processor Thermal Control % Sensors – Next Steps
    • 5.2.4 Processor DTS Thermal Margin Sensors
    • 5.2.5 Discrete Thermal Sensors
    • 5.2.6 DIMM Thermal Trip Sensors
      • 5.2.6.1 DIMM Thermal Trip Sensors – Next Steps
  • 5.3 System Air Flow Monitoring Sensor
• 6. Processor Subsystem
  • 6.1 Processor Status Sensor
  • 6.2 Catastrophic Error Sensor
  • 6.3 CPU Missing Sensor
    • 6.3.1 CPU Missing Sensor – Next Steps
  • 6.4 Quick Path Interconnect Sensors
    • 6.4.1 QPI Link Width Reduced Sensor
      • 6.4.1.1 QPI Link Width Reduced Sensor – Next Steps
    • 6.4.2 QPI Correctable Error Sensor
      • 6.4.2.1 QPI Correctable Error Sensor – Next Steps
    • 6.4.3 QPI Fatal Error and Fatal Error #2
      • 6.4.3.1 QPI Fatal Error and Fatal Error #2 – Next Steps
  • 6.5 Processor ERR2 Timeout Sensor
    • 6.5.1 Processor ERR2 Timeout – Next Steps
  • 6.6 Processor MSID Mismatch Sensor
    • 6.6.1 Processor MSID Mismatch Sensor – Next Steps
• 7. Memory Subsystem
  • 7.1 Memory RAS Configuration Status
  • 7.2 Memory RAS Mode Select
  • 7.3 Mirroring Redundancy State
    • 7.3.1 Mirroring Redundancy State Sensor – Next Steps
  • 7.4 Sparing Redundancy State
    • 7.4.1 Sparing Redundancy State Sensor – Next Steps
  • 7.5 ECC and Address Parity
    • 7.5.1 Memory Correctable and Uncorrectable ECC Error
    • 7.5.2 Memory Address Parity Error
      • 7.5.2.1 Memory Address Parity Error Sensor – Next Steps
• 8. PCI Express* and Legacy PCI Subsystem
  • 8.1 PCI Express* Errors
    • 8.1.1 Legacy PCI Errors
      • 8.1.1.1 Legacy PCI Error Sensor – Next Steps
    • 8.1.2 PCI Express* Fatal Errors and Fatal Error #2
      • 8.1.2.1 PCI Express* Fatal Error and Fatal Error #2 Sensor – Next Steps
    • 8.1.3 PCI Express* Correctable Errors
      • 8.1.3.1 PCI Express* Correctable Error Sensor – Next Steps
• 9. System BIOS Events
  • 9.1 System Events
    • 9.1.1 System Boot
    • 9.1.2 Timestamp Clock Synchronization
  • 9.2 System Firmware Progress (Formerly Post Error)
    • 9.2.1 System Firmware Progress (Formerly Post Error) – Next Steps
• 10. Chassis Subsystem
  • 10.1 Physical Security
    • 10.1.1 Chassis Intrusion
    • 10.1.2 LAN Leash Lost
  • 10.2 FP (NMI) Interrupt
    • 10.2.1 FP (NMI) Interrupt – Next Steps
  • 10.3 Button Sensor
• 11. Miscellaneous Events
  • 11.1 IPMI Watchdog
  • 11.2 SMI Timeout
    • 11.2.1 SMI Timeout – Next Steps
  • 11.3 System Event Log Cleared
  • 11.4 System Event – PEF Action
    • 11.4.1 System Event – PEF Action – Next Steps
  • 11.5 BMC Watchdog Sensor
    • 11.5.1 BMC Watchdog Sensor – Next Steps
  • 11.6 BMC FW Health Sensor
    • 11.6.1 BMC FW Health Sensor – Next Steps
  • 11.7 Firmware Update Status Sensor
  • 11.8 Add-In Module Presence Sensor
    • 11.8.1 Add-In Module Presence – Next Steps
  • 11.9 Intel® Xeon Phi™ Coprocessor Management Sensors
    • 11.9.1 Intel® Xeon Phi™ Coprocessor (MIC) Thermal Margin Sensors
    • 11.9.2 Intel® Xeon Phi™ Coprocessor (MIC) Status Sensors
      • 11.9.2.1 Intel® Xeon Phi™ Coprocessor (MIC) Status Sensors Next Steps
• 12. Hot-Swap Controller Backplane Events
  • 12.1 HSC Backplane Temperature Sensor
  • 12.2 Hard Disk Drive Monitoring Sensor
  • 12.3 Hot-Swap Controller Health Sensor
    • 12.3.1 HSC Health Sensor – Next Steps
• 13. Manageability Engine (ME) Events
  • 13.1 ME Firmware Health Event
    • 13.1.1 ME Firmware Health Event – Next Steps
  • 13.2 Node Manager Exception Event
    • 13.2.1 Node Manager Exception Event – Next Steps
  • 13.3 Node Manager Health Event
    • 13.3.1 Node Manager Health Event – Next Steps
  • 13.4 Node Manager Operational Capabilities Change
    • 13.4.1 Node Manager Operational Capabilities Change – Next Steps
  • 13.5 Node Manger Alert Threshold Exceeded
    • 13.5.1 Node Manger Alert Threshold Exceeded – Next Steps
• 14. Microsoft Windows* Records
  • 14.1 Boot up Event Records
  • 14.2 Shutdown Event Records
  • 14.3 Bug Check / Blue Screen Event Records
• 15. Linux* Kernel Panic Records