Motorola TMS320C6711D - Manual (Page 91)

TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292 − OCTOBER 2005
91 POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP †‡ (see Figure 46)
NO.
GDPA−167
ZDPA−167
−200
−250 UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5 * tc(CKRX) −1¶ ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
CLKR int 9
ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
CLKR ext 1
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR int 6
ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR ext 3
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int 8
ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR ext 0
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int 3
ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR ext 4
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX int 9
ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX ext 1
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX int 6
ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX ext 3
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
§ The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0)
in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.