MiTAC 7521 PLUS/N - Manual (Page 9)

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7521 7521 Plus / N N/B MAINTENANCE Plus / N N/B MAINTENANCE
Integrated Host-to-PCI Bridge
Zero Wait State Burst Cycles
CPU-to-PCI Pipeline Access
256B to 4KB PCI Burst Length for PCI Masters
PCI Master Initiated Graphical Texture Write Cycles Re-mapping
Reassembles PCI Burst Data Size into Optimized Block Size
Fast PCI IDE Master/Slave Controller
Supports PCI Bus Mastering
Native Mode and Compatibility Mode
PIO Mode 0, 1, 2, 3, 4
Multiword DMA Mode 0, 1, 2
Ultra DMA 33/66/100
Two Independent IDE Channels Each with 16 DW FIFO
Virtual PCI-to-PCI Bridge
Integrated Ultra AGP VGA for Hardware 2D/3D Video/Graphics Accelerators
Supports Tightly Coupled 64 Bits Host Interface to VGA to Speed Up GUI Performance and Video Playback Frame Rate
AGP v. 2.0 Compliant
Zero-Wait-State 128x4 Post-Write Buffer with Write Combine Capability
Zero-Wait-State 128x4 2-Way Read Ahead Cache Capability
Re-locatable Memory-Mapped and I/O Address Decoding
Flexible Design Shared Frame Buffer Architecture for Display Memory
Shared System Memory Area up to 64MB
Built-in 8K Bytes Texture Cache