Sun Microsystems SME5224AUPA-400 - Manual (Page 3)

3
400 MHz CPU, 4.0 MB E-Cache
UltraSPARC ™ -II CPU Module
SME5224AUPA-400
Advanced Version
July 1999 Sun Microsystems, Inc
D ATA B UFFER D ESCRIPTION
UltraSPARC-II Data Buffer (UDB-II)
The UltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for
a UPA Interconnect system bus width of 128 Data + 16 ECC.
There is a bidirectional flow of information between the external cache of the CPU and the 144-bit UPA inter-
connect. The information flow is linked through the UDB-II, it includes: cache fill requests, writeback data for
dirty displaced cache lines, copyback data for cache entries requested by the system, non-cacheable loads and
stores, and interrupt vectors going to and from the CPU.
Each UDB-II has a 64-bit interface plus eight parity bits on the CPU side, and a 64-bit interface plus eight error
correction code (ECC) bits on the system side.
The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipe-
line frequency).
E XTERNAL C ACHE D ESCRIPTION
The external cache is connected to the E-cache data bus. Nine SRAM chips are used to implement the four
megabyte cache. One SRAM is used as the tag SRAM and eight are used as data SRAMs. The tag SRAM is
128K x 36, while the data SRAMs are 256K x 18. All nine SRAMs operate in synchronous register-latch mode.
The SRAM interface to the CPU runs at one-half of the frequency of the CPU pipeline. The SRAM signals
operate at 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input.
[1]
1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache
interface.