Sun Microsystems SME5224AUPA-400 - Manual (Page 32)

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SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
UltraSPARC ™ -II CPU Module
July 1999 Sun Microsystems, Inc
M ODULE C OMPONENT O VERVIEW
The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the
following components:
• UltraSPARC™-II CPU at 400 MHz
• UltraSPARC-II Data Buffer (UDB-II)
• 4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM
• Clock Buffer: MC100LVE210
• DC-DC regulator (2.6V to 1.9V)
• Module Airflow Shroud
Block Diagram
The module block diagram for the UltraSPARC™–II, 400 MHz CPU, 4 Mbyte E-cache module
is illustrated in Figure 1.
Figure 1. Module Block Diagram
Tag SRAM
128K x 36
SRAM
256K x 18
Tag SRAM ADDR [17:0] + Control
Tag SRAM DATA [24:0]
UltraSPARC-II
CPU
UDB-II UDB-II
SRAM ADDR [19:0] + Control
DATA [71:0] DATA [143:72]
UDB-II
Control
UPA Connector
Clock Buffer
Clocks
UPA ADDR [35:0] + Control
SRAM
256K x 18
DC-DC
Regulator
2.6V
1.9V
UPA_DATA [143:0]