Sun Microsystems SME5224AUPA-400 - Manual (Page 50)

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SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
UltraSPARC ™ -II CPU Module
July 1999 Sun Microsystems, Inc
JTAG T ESTABILITY
The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), implements the IEEE 1149.1
standard to aid in board level testing. Boundary Scan Description Language (BSDL) files are available for all
the active devices on the module, except the clock buffer.
AC Characteristics - JTAG Timing
Symbol Parameter Signals Conditions
400 MHz CPU
10 MHz TCK
Units Min Typ Max
t
W
(TRST) Test reset pulse width TRST [1]
1. TRST is an asynchronous reset.
– – – ns
t
SU
(TDI) Input setup time to TCK TDI – 3 – ns
t
SU
(TMS) Input setup time to TCK TMS – 4 – ns
t
H
(TDI) Input hold time to TCK TDI – 1.5 – ns
t
H
(TMS) Input hold time to TCK TMS – 1.5 – ns
t
PD
(TDO) Output delay from TCK [2]
2. TDO is referenced from falling edge of TCK.
TDO I
OL
= 8 mA
I
OH
= -4 mA
C
L
= 35 pF
V
LOAD
= 1.5V
– 6 – ns
t
OH
(TDO) Output hold time from TCK [2] TDO 3 – – ns