Seagate Ultra 320 - Manual (Page 39)

Parallel SCSI Interface Product Manual, Rev. A ) 25
Table 9: SCSI Fast-160 and fast 320 non-compensatable timing budget in nanoseconds
Item Fast-160 Fast-320 Comments
REQ(ACK) period 12.5 6.25 From Table 7
Transfer period 6.25 3.125 REQ(ACK) period / 2
Transmitter and receiver errors:
Total
Errors
Post
Compen
sation
Total
Errors
Post
Compen
sation
Worst case total of + and - time
shift except where noted
Transmitter errors:
REQ(ACK) period tolerance / 2 0.06 0.06 0.06 0.06 Tolerance of transmitter plus mea-
surement error
b
Clock Jitter 0.25 0.25 0.25 0.50
System noise at transmitter 0.25 0.25 0.2 0.2 Time impact
Transmitter chip skew 0.75 0 0.75 0
Transmitter trace skew
0.2 0 0.2 0
Transmit time asymmetry 0.50 0.50 0.50 0 Compensated for on fast-320
SCSI devices
Total transmitter error budget: 2.01 1.06 1.96 0.51
Receiver errors:
System noise at receiver 0.25 0.25 0.2 0.2 Time impact
Chip noise in receiver 0.2 0.2 0.2 0.2 Time impact
Receiver chip skew 0.75 0 0.75 0
Receiver trace skew 0.2 0 0.2 0
Receiver time asymmetry 0.35 0.35 0.35 0
Residual skew error 0 0.3 0 0.2 After skew compensation
Strobe offset tolerance
0 0.5 0 0.2
Accuracy of centering strobe
Offset induced time asymmetry N/A
a
N/A
a 0.8 0.2
Time impact from cumulative D.C.
offsets at receiver
Receiver amplitude time skew 0.2 0.2 0.2 0.05
Total receiver error budget: 1.95 1.8 2.7 1.05
Total Transmitter + receiver error
budget:
3.96 2.86 4.44 1.53
Total timing error budget for
interconnect and system margin:
2.29 3.39 -1.535 1.565
Transfer period - (total transmitter
+ total receiver error budget)
a Timing budgets in some previous standards neglected asymmetry & detection ambiguity and
lumps chip noise, clock jitter, crosstalk time shift, noise, ISI and receiver amplitude skew into
other terms (e.g., signal distortion skew) and/or ignores the effects.
b
Tolerance adjusted for half cycle (i.e., transfer period)