Post codes – Sun Microsystems Sun Fire X4240 User Manual
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Appendix A
Event Logs and POST Codes
31
POST Codes
contains descriptions of each of the POST codes, listed in the same order
in which they are generated. These POST codes appear as a four-digit string that is a
combination of two-digit output from primary I/O port 80 and two-digit output
from secondary I/O port 81. In the POST codes listed in
, the first two
digits are from port 81 and the last two digits are from port 80.
TABLE A-1
POST Codes
Post Code
Description
00d0
Coming out of POR, PCI configuration space initialization, enabling 8111’s SMBus.
00d2
Disable cache, full memory sizing, and verify that flat mode is enabled.
00d3
Memory detections and sizing in boot block, cache disabled, IO APIC enabled.
01d4
Test base 512KB memory. Adjust policies and cache first 8MB.
01d5
Bootblock code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
01d6
Key sequence and OEM specific method is checked to determine if BIOS recovery is
forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
01d7
Restoring CPUID; moving bootblock-runtime interface module to RAM; determine
whether to execute serial flash.
01d8
Uncompressing runtime module into RAM. Storing CPUID information in memory.
01d9
Copying main BIOS into memory.
01da
Giving control to BIOS POST.
0004
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. If the CMOS checksum is bad, update CMOS with power-on default values.
00c2
Set up boot strap processor for POST. This includes frequency calculation, loading BSP
microcode, and applying user requested value for GART Error Reporting setup question.
00c3
Errata workarounds applied to the BSP (#78 & #110).
00c6
Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata
#106, #107, #69, and #63 if appropriate.
00c7
HT sets link frequencies and widths to their final values.
000a
Initializing the 8042 compatible Keyboard Controller.
000c
Detecting the presence of Keyboard in KBC port.
000e
Testing and initialization of different Input Devices. Traps the INT09h vector, so that the
POST INT09h handler gets control for IRQ1.
8600
Preparing CPU for booting to OS by copying all of the context of the BSP to all application
processors present. NOTE: APs are left in the CLI HLT state.