Sun Microsystems Sun Fire X4240 - Manual (Page 35)

Appendix A Event Logs and POST Codes 25
Power-On Self-Test (POST)
The system BIOS provides a rudimentary power-on self-test. The basic devices
required for the server to operate are checked, memory is tested, the LSI 1064 disk
controller and attached disks are probed and enumerated, and the two Intel dual
Gigabit Ethernet controllers are initialized.
The progress of the self-test is indicated by a series of POST codes. These codes are
displayed at the bottom right corner of the system’s VGA screen (once the self-test
has progressed far enough to initialize the system video). However, the codes are
displayed as the self-test runs and scroll off of the screen too quickly to be read. An
alternate method of displaying the POST codes is to redirect the output of the
console to a serial port (see
“Redirecting Console Output” on page 26 ).
How BIOS POST Memory Testing Works
The BIOS POST memory testing is performed as follows:
1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is
shadowed (that is, copied from ROM to DRAM).
2. Once executing out of DRAM, the BIOS performs a simple memory test (a
write/read of every location with the pattern 55aa55aa).
Note – Enabling Quick Boot causes the BIOS to skip the memory test. See
“Changing POST Options” on page 28 for more information.
Note – Because the server can contain up to 64 MB of memory (128 MB for the
X4440), the memory test can take several minutes. You can cancel POST testing by
pressing any key during POST.
3. The BIOS polls the memory controllers for both correctable and uncorrectable
memory errors and logs those errors into the service processor.