ST & T UPSD3212C - Manual (Page 108)

uPSD3212A, uPSD3212C, uPSD3212CV
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Decode PLD (DPLD)
The DPLD, shown in Figure
55 , is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
–
4 Sector Select (FS0-FS3) signals for the
primary Flash memory (three product terms
each)
– 2 Sector Select (CSBOOT0-CSBOOT1)
signals for the secondary Flash memory (three
product terms each)
– 1 internal SRAM Select (RS0) signal (two
product terms)
– 1 internal CSIOP Select signal (selects the
PSD MODULE registers)
– 2 internal Peripheral Select signals
(Peripheral I/O Mode).
Figure 55. DPLD Logic Array
Note: 1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
(INPUTS)
(20)
(8)
(16)
(1)
PDN (APD OUTPUT)
I /O PORTS (PORT A,B,C)1
(8)
PGR0 - PGR7
(8) MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]2
(2)
(4)
PD[2:1]
PSEN, RD, WR, ALE2
(1)
(1)
RESET 2
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
4 PRIMARY FLASH
MEMORY SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
FS0
3
3
3
3
3
3
2
AI07436
FS1
FS2
FS3
1
1
1