ST & T UPSD3212C - Manual (Page 107)

107/163
uPSD3212A, uPSD3212C, uPSD3212CV
Figure 54. PLD Diagram
Note: 1. Ports A is not available in the 52-pin package
PLD INPUT BUS
8
INPUT MACROCELL & INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
CPLD
PT
ALLOC.
MACROCELL
ALLOC.
MCELLAB
MCELLBC
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
20 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
PRIMARY FLASH MEMORY SELECTS
2 PORT D INPUTS
TO PORT A OR B1
TO PORT B OR C
DATA
BUS
4
8
8
2
1
1
2
EXTERNAL CHIP SELECTS
TO PORT D
2
16
20
OUTPUT MACROCELL FEEDBACK
AI07435
73
73