Renesas Emulation Pod M30620T2-RPD-E - Manual (Page 47)

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5.2 Operation Timing in Memory Expansion and Microprocessor Modes (5 V)
(1) Separate Bus, No-Wait
Table 5.2 and Figure 5.1 show the bus timing in the memory expansion mode and the microprocessor
mode (separate bus, no-wait).
Table 5.2 Memory expansion mode and microprocessor mode (separate bus, no-wait)
Td (DB-WR)=
10 9
f(BCLK) x 2
-40 [ns]
*1 Calculated by the following formula according to the frequency of BCLK.
Td (BCLK-AD)
Th (BCLK-AD)
Th (RD-AD)
Th (WR-AD)
Td (BCLK-CS)
Th (BCLK-CS)
Td (BCLK-ALE)
Th (BCLK-ALE)
Td (BCLK-RD)
Th (BCLK-RD)
Td (BCLK-WR)
Th (BCLK-WR)
Td (BCLK-DB)
Th (BCLK-DB)
Td (DB-WR)
Th (WR-DB)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
Min.
4
0
0
4
-4
0
0
4
(*1)
0
Max.
25
25
25
25
25
40
Min. Max.
Actual MCU
[ns]
This product
[ns]
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