Oki 4M - Manual (Page 17)

2 - 4
Controls DRAM.
Built-in Device Function
DRAM controller
Transfers image data from Parallel I/F to DRAM, from DRAM to a video output port and
between CPU and DRAM.
Video output port
LED STB output port
Generates various control timings for monitoring paper feeding and a paper size.
Inputs the feedback signals from a high-voltage generation circuit and thermistor signal.
DMA controller
Parallel interface controller
Timer
I/O port
A/D converter
Controls the parallel interface.
Controls LED head.
Inputs and outputs the sensor signals and motor signals, etc.
Also performs I/O for EEPROM.
2.1 Main Control Board
The main control board consists of a one-chip CPU, a program ROM, a DRAM, an EEPROM, a
host interface circuit, and a mechanism driving circuit. The mechanism driving circuit consists of
a LED head, a main motor, and an electromagnetic clutch.
(1) One-chip CPU
The one-chip CPU is a custom CPU (8-bit internal bus, 8-bit external bus, 10-MHz clock)
incorporating mask ROM and CPU peripheral devices. This CPU has the functions listed in
the table below.
(2) Program ROM
Program ROM contains a program for the equipment. EPROM is used as program ROM.
When mask ROM in the one-chip CPU explained in (1) above is valid, the EPROM is not
mounted. (For details on short wiring setting, see Section 7.2.)
(3) DRAM
DRAM is used as resident memory.
(4) EEPROM
EEPROM holds the following data:
• Menu data
• Counter value
• Adjustment value
(5) Parallel interface
The parallel interface receives parallel data from the host; it conforms to the IEEE1284
specification.
(6) Macintosh interface <only OKIPAGE 4m>
Mcintosh interfacce receives serial data from the host ; it conforms to the IEEE1284.