Toshiba 3006GAL - Manual (Page 151)

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11.2 PIO data out commands
Commands for this class are:
• (FORMAT TRACK)
• WRITE BUFFER
• WRITE MULTIPLE
• WRITE MULTIPLE EXT
• WRITE SECTOR(S) (with and without retry)
• WRITE SECTOR(S) EXT
• WRITE VERIFY
• SECURITY DISABLE PASSWORD
• SECURITY ERASE UNIT
• SECURITY SET PASSWORD
• SECURITY UNLOCK
• SET MAX SET PASSWORD
• SMART Write Log Sector
• DOWNLOAD MICROCODE
PIO data out protocol:
a) The host writes any required command parameters to the Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low and Device/Head registers.
b) The host writes the command code to the Command register.
c) The drive sets the BSY bit .
d) For each sector (or block) of data to be transferred:
1) When the drive is ready to receive a sector (or block) of data from the host, it sets the DRQ bit and clears
the BSY bit.
2) The host writes a sector (or block) of data via the Data Register.
3) After receiving the sector (or block) , the drive clears the DRQ bit and sets the BSY bit.
4) When the drive has finished processing the sector (or block) , it sets the DRQ bit and clears the BSY bit
and asserts INTRQ.
5) After detecting INTRQ, the host reads the Status register.
6) The drive negates INTRQ in response to the Status register being read.
The drive negates INTRQ in response to the Status register being read.
The Write Multiple command transfers one block ( the number of sectors is defined by the Set Multiple
command ) of data for each interrupt. The other commands transfer one sector of data for each interrupt.
If the drive detects an invalid parameter in register setting, the drive clears the BSY bit and sets the ERR bit
in the Status register and sets the ABRT bit in the Error register and asserts INTRQ to terminate the
command execution.
If an unrecoverable error occurs, the drive sets the DRQ bit and clears the BSY bit and sets the ERR bit and
stores the error status in Error register and report the address information of the sector with error to Sector
Number, Cylinder High, Cylinder Low and Device/Head registers and asserts INTRQ.