Texas Instruments VLYNQ Port - Manual (Page 12)

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2.2 Signal Descriptions
2.3 Pin Multiplexing
2.4 Protocol Description
Peripheral Architecture
The VLYNQ module on the DM644x device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pin
multiplexing registers control the configuration. See the pin multiplexing information in the device-specific
data manual.
If the configured width does not match the number of transmit/receive lines that are available on the
remote device, negotiation between the two VLYNQ devices automatically configures the width (see
Section 2.7 ).
The VLYNQ interface signals are shown in Table 1 .
Table 1. VLYNQ Port Pins
Pin Name Signal Name I/O Description
VLYNQ_CLOCK VLYNQ serial clock I/O The VLYNQ reference clock supports the internally or externally generated
clock.
VLYNQ_SCRUN VLYNQ serial clock I/O The VLYNQ serial clock run request allows remote requests for the VLYNQ
run request serial clock to be turned off for system power management.
(Active low) Low: The request VLYNQ serial clock is active.
High: The VLYNQ serial clock is requested to be high when all transactions are
complete.
VLYNQ_RXD[0:3] VLYNQ receive data I VLYNQ receive data is synchronous with the VLYNQ serial clock.
VLYNQ_TXD[0:3] VLYNQ transmit data O VLYNQ transmit data is synchronous with the VLYNQ serial clock.
The VLYNQ signals share pins on the processor package with other processor functions. The VLYNQ
module pins are not enabled at reset. In order to change the default function of device pins at reset, the
pin multiplexing registers (PINMUXn) must be configured appropriately. See the pin multiplexing
information in the device-specific data manual for more detailed information on the processor pin
multiplexing and configuration registers.
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet
delineation and control.
Appendix A provides general information on 8b/10b coding definitions and their implementation within the
VLYNQ module in the DM644x device.
VLYNQ Port 12 SPRUE36A – September 2007
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