Texas Instruments VLYNQ Port - Manual (Page 21)

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2.11 Reset Considerations
2.11.1 Software Reset Considerations
2.11.2 Hardware Reset Considerations
2.12 Interrupt Support
2.12.1 Interrupt Events and Requests
Peripheral Architecture
Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is
included with the device. For more information, refer to the power management section (
Section 2.14 ).
Additionally, there is a software reset (the reset bit in the VLYNQ control register, CTRL) within the
peripheral itself. Writing a 1 to the reset bit resets all of the internal state machines of the VLYNQ module,
the serial interface is disabled, and the link is lost. The VLYNQ module remains in reset until the software
clears the bit.
Note: When setting the reset bit, the VLYNQ status register (STAT) value is the only value that is
set to the default value. All of the other VLYNQ memory-mapped registers retain their values
prior to the software reset.
When a hardware reset occurs, the VLYNQ peripheral resets its register values to the default values and
the serial interface is disabled. After a hardware reset, the VLYNQ memory mapped registers and any
chip-level registers that are associated with VLYNQ (for example, pin multiplexing registers) must be
configured appropriately before data transmission can resume.
CAUTION
Be cautious when only resetting one of the VLYNQ devices after two or more
VLYNQ devices have established a link. If only one of the VLYNQ devices is in
reset, then no data activity can occur across the serial interface during the time
of reset.
The VLYNQ module interrupt VLQINT is mapped to the ARM interrupt controller (ARM INT31). For more
information on the ARM interrupt controller (AINTC), see the TMS320DM644x DMSoC ARM Subsystem
Reference Guide (
SPRUE14 ).
Interrupts generate when bits are set in the VLYNQ interrupt pending/set register (INTPENDSET). Bits are
set in the INTPENDSET register when any of the following occur:
•
Writing directly to the INTPENDSET
•
Remote interrupt (via the serial interrupt packet)
•
Serial bus error
When the VLYNQ interrupt pending/set register (INTPENDSET) is a non-zero value, the method of
forwarding the interrupt status depends on the state of the INTLOCAL bit in the VLYNQ control register
(CTRL).
When INTLOCAL = 0, the contents of INTPENDSET are inserted into an interrupt packet and sent over
the serial interface. When packet transmission completes, the associated bits clear in INTPENDSET.
When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register
(INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line, causing
the VLYNQINT to pulse.
If the system writes to INTSTATCLR while interrupts are still pending, a new VLQINT interrupt is
generated.
The VLYNQ interrupt generation mechanism is shown in Figure 8 .
SPRUE36A – September 2007 VLYNQ Port 21
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