15 receive address map size 4 register (rams4), 16 receive address map offset 4 register (ramo4), Rams4) – Texas Instruments VLYNQ Port User Manual

Page 37: Descriptions, Section 3.15, Section 3.16

Advertising
background image

www.ti.com

3.15 Receive Address Map Size 4 Register (RAMS4)

3.16 Receive Address Map Offset 4 Register (RAMO4)

VLYNQ Port Registers

The receive address map size 4 register (RAMS4) is used to identify the intended destination of inbound
serial packets. The RAMS4 is shown in

Figure 23

and described in

Table 21

.

Figure 23. Receive Address Map Size 4 Register (RAMS4)

31

2

1

0

RXADRSIZE4

Reserved

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. Receive Address Map Size 4 Register (RAMS4) Field Descriptions

Bit

Field

Value

Description

31-2

RXADRSIZE4

0-3FFF FFFFh

The RXADRSIZE4 field is used to determine if receive packets are destined for the fourth of
four mapped address regions. RXADRSIZE4 is compared with the address contained in the
receive packet. If the receive packet address is less than the value in RXADRSIZE4, the
packet address is added to the receive address map offset 4 register (RAMO4) to obtain the
translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

The receive address map offset 4 register (RAMO4) is used with the receive address map size 4 register
(RAMS4) to translate receive packet addresses to local device configuration bus addresses. The RAMS4
is shown in

Figure 24

and described in

Table 22

.

Figure 24. Receive Address Map Offset 4 Register (RAMO4)

31

2

1

0

RXADROFFSET4

Reserved

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. Receive Address Map Offset 4 Register (RAMO4) Field Descriptions

Bit

Field

Value

Description

31-2

RXADROFFSET4

0-3FFF FFFFh

The RXADROFFSET4 field is used with the receive address map size 4 register (RAMS4)
to determine the translated address for serial data. If the receive packet address is less
than the value in RAMS4, the packet address is added to the contents of this register to
obtain the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

SPRUE36A – September 2007

VLYNQ Port

37

Submit Documentation Feedback

Advertising