Xilinx LOGICORE UG144 - Manual (Page 28)

28 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 2: Core Architecture R
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Management Interface (Optional)
Table 2-4 describes the optional signals used by the client to access the management
features of the GEMAC core. See “Using the Optional Management Interface,” on page 77 .
MAC Unicast Address (Optional)
Table 2-5 describes the alternative method of access to the unicast address registers when
the optional Management Interface is not present.
Table 2-4: Optional Management Interface Signal Pinout
Signal Direction
Clock
Domain
Description
host_clk Input n/a Clock for the Management
Interface; must be 10 MHz or
above.
host_opcode[1:0] Input host_clk Defines operation to be performed
over MDIO interface. Bit 1 is also
used as a read/write control
signal for configuration register
access.
host_addr[9:0] Input host_clk Address of register to be accessed.
host_wr_data[31:0] Input host_clk Data to write to register .
host_rd_data[31:0] Output host_clk Data read from register.
host_miim_sel Input host_clk When asserted, the MDIO
interface is accessed. When not
asserted, the configuration
registers are accessed.
host_req Input host_clk Used to signal a transaction on the
MDIO interface.
host_miim_rdy Output host_clk When high, the MDIO interface
has completed any pending
transaction and is ready for a new
transaction.
Table 2-5: Optional MAC Unicast Address Signal Pinout
Signal Direction Description
mac_unicast_address[47:0] Input Used to assess the MAC unicast
address registers when the
Management Interface is not used
Note: All bits are registered on input but may be treated as asynchronous inputs.