Xilinx LOGICORE UG144 - Manual (Page 92)

92 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 8: Configuration and Status R
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62 “Flow Control
Configuration
Word”
bit 30
gtx_clk Receive Flow Control Enable . When this bit
is ‘1,’ received flow control frames will inhibit
the transmitter operation. When at ‘0,’
received flow frames are passed up to the
client.
63 “Receiver
Configuration
Word 1”
bit 25
gtx_clk Length/Type Error Check Disable . When
this bit is set to ‘1,’ the core will not perform
the length/type field error checks as
described in
“Length/Type Field Error
Checks,” on page 43 . When this bit is set to
‘0,’ the length/type field checks will be
performed: this is normal operation.
64 “Address Filter
Mode”
bit 31
gmii_rx_clk Address Filter Enable . When this bit is ‘0,’
the Address Filter is enabled. If it is set to ‘1,’
the Address Filter will operate in
promiscuous mode.
66:65 n/a n/a This input is unused.
67 “Receiver
Configuration
Word 1”
bit 24
gtx_clk Control Frame Length Check Disable When
this bit is set to ‘1,’ the core will not mark
control frames as ‘bad’ if they are greater than
the minimum frame length.
Table 8-13: Configuration Vector Bit Definition (Continued)
Bit(s)
Configuration
Register cross
reference
Clock Description