Xilinx LOGICORE UG144 - Manual (Page 88)

88 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 8: Configuration and Status R
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Read Transaction
Figure 8-7 shows a Read transaction; this is defined by OP=”10”. The addressed MMD
(PHYAD) device returns the 16-bit word from the register at REGAD.
For details of the register map of MMD (PHY layer devices) and a detailed description of
the operation of the MDIO Interface itself, see IEEE 802.3-2005.
Accessing MDIO With GEMAC
More information about MDIO with GEMAC can be found in the following sections of this
guide:
• For the GEMAC port definition of the MDIO, see “MDIO Interface” in Chapter 2
• “Connecting the MDIO to an Internally Integrated PHY,” on page 76
• “Connecting the MDIO to an External PHY,” on page 76
The management interface is also used to access the MDIO interface of the GEMAC core.
The MDIO interface supplies a clock to the connected PHY, mdc. This clock is derived from
the host_clk signal using the value in the Clock Divide[4:0] configuration register.
The frequency of mdc is given by the following equation:
The frequency of mdc given by this equation should not exceed 2.5 MHz to comply with
the IEEE 802.3-2005 specification for this interface. To prevent mdc from being out of
specification, the Clock Divide[4:0] value powers up at 00000. While this value is in
the register, it is impossible to enable the MDIO interface.
For details of the register map of PHY layer devices and a detailed description of the
operation of the MDIO interface itself, see IEEE 802.3-2005.
Figure 8-7: MDIO Read Transaction
Z 1 1 1 0 1 0 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 Z 0 D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 Z Z Z
mdc
mdio
IDLE IDLE 32 bits
PRE
ST OP PRTAD REGAD TA 16-bit READ DATA
STA drives MDIO MMD drives MDIO
f
MDC
f
HOST_CLK
1 Clock Divide[4:0] +
( ) 2 Ч
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