Rainbow Electronics AT89LP214 - Manual (Page 66)

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3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
The In-System Programming Interface is the only means of externally programming the
AT89LP213/214 microcontroller. The ISP Interface can be used to program the device both in-
system and in a stand-alone serial programmer. The ISP Interface does not require any clock
other than SCK and is not limited by the system clock frequency. During In-System program-
ming the system clock source of the target device can operate normally.
When designing a system where In-System Programming will be used, the following observa-
tions must be considered for correct operation:
• The ISP interface uses the SPI clock mode 0 (CPOL = 0,CPHA = 0) exclusively with a
maximum frequency of 5 MHz.
• The AT89LP213/214 will enter programming mode only when its reset line (RST) is
active (low). To simplify this operation, it is recommended that the target reset can be
controlled by the In-System programmer. To avoid problems, the In-System programmer
should be able to keep the entire target system reset for the duration of the programming
cycle. The target system should never attempt to drive the four SPI lines while reset is active.
• The RST input may be disabled to gain an extra I/O pin. In these cases the RST pin will
always function as a reset during power up. To enter programming the RST pin must be
driven low prior to the end of Power-On Reset (POR). After POR has completed the device
will remain in ISP mode until RST is brought high. Once the initial ISP session has ended, the
power to the target device must be cycled OFF and ON to enter another session.
• The SS pin should not be left floating during reset if ISP is enabled.
• The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP
Fuse is disabled, ISP may only be entered at POR.
23.2 Memory Organization
The AT89LP213/214 offers 2K bytes of In-System Programmable (ISP) nonvolatile Flash code
memory. In addition, the device contains a 64-byte User Signature Array and a 32-byte read-
only Atmel Signature Array. The memory organization is shown in
Table 23-1 and Figure 23-2 .
The memory is divided into pages of 32 bytes each. A single read or write command may only
access a single page in the memory. Each memory type resides in its own address space and is
accessed by commands specific to that memory. However, all memory types share the same
page size.
User configuration fuses are mapped as a row in the memory, with each byte representing one
fuse. From a programming standpoint, fuses are treated the same as normal code bytes except
they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the
appropriate locations in the fuse row. However, to disable a fuse, i.e. set it to FFh, the entire
fuse row must be erased and then reprogrammed. The programmer should read the state of all
the fuses into a temporary location, modify those fuses which need to be disabled, then issue a
Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi-
lar manner to fuses except they may only be erased (unlocked) by Chip Erase.
Table 23-1. Code Memory Sizes
Device # Code Size Page Size # Pages Address Range
AT89LP213 2K bytes 32 bytes 64 0000H - 07FFH
AT89LP214 2K bytes 32 bytes 64 0000H - 07FFH