Rainbow Electronics AT45DQ321 - Manual (Page 11)

11 AT45DQ321 [ADVANCE DATASHEET]
DS-45DQ321-031–DFLASH–12/2012
5.8 Dual-output Read Array (3Bh Opcode)
The Dual-output Read Array command is similar to the Continuous Array Read command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Continuous Array Read command however, the Dual-output Read Array
command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-output Read Array command can be used at any clock frequency up to the maximum specified by f
SCK
. To
perform a Dual-output Read Array using the standard DataFlash page size (528 bytes), the CS pin must first be asserted,
and then an opcode of 3Bh must be clocked into the device followed by three address bytes and one dummy byte. The
first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array to read and the
last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page.
To perform a Dual-output Read Array using the binary page size (512 bytes), the opcode 3Bh must be clocked into the
device followed by three address bytes (A21 - A0) and one dummy byte.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the I/O
1
and I/O
0
pins. The data is always output with the MSB of a byte first, and the MSB is always
output on the I/O
1
pin. During the first clock cycle, bit seven of the first data byte will be output on the I/O
1
pin while bit six
of the same data byte will be output on the I/O
0
pin. During the next clock cycle, bits five and four of the first data byte will
be output on the I/O
1
and I/O
0
pins, respectively. The sequence continues with each byte of data being output after every
four clock cycles.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Dual-output Read Array the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state both the I/O
1
and I/O
0
pins. The Dual-
output Dual-output Read Array bypasses both data buffers and leaves the contents of the buffers unchanged.
5.9 Quad-output Read Array (6Bh Opcode)
The Quad-output Read Array command is similar to the Dual-output Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Dual-output Read Array command however, the Quad-output Read Array
command allows four bits of data to be clocked out of the device on every clock cycle rather than two.
Note: The QE bit in the Configuration Register must be previously set in order for any Quad-I/O command (i.e.
Quad-output Read Array command) to be enabled and for the RESET and WP pins to be converted to I/O
data pins.
The Quad-output Read Array command can be used at any clock frequency up to the maximum specified by f
SCK
. To
perform a Quad-output Read Array using the standard DataFlash page size (528 bytes), the CS pin must first be
asserted, and then an opcode of 6Bh must be clocked into the device followed by three address bytes and one dummy
byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array to read
and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page.
To perform a Quad-output Read Array using the binary page size (512 bytes), the opcode 6Bh must be clocked into the
device followed by three address bytes (A21 - A0) and one dummy byte.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O
3-0
pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O
3
pin. During the first clock cycle, bit seven of the first data byte will be output on the I/O
3
pin while bits six, five, and four of
the same data byte will be output on the I/O
2
, I/O
1
, and I/O
0
pins, respectively. During the next clock cycle, bits three,
two, one, and zero of the first data byte will be output on the I/O
3
, I/O
2
, I/O
1
and I/O
0
pins, respectively. The sequence
continues with each byte of data being output after every two clock cycles.