Rainbow Electronics AT45DQ321 - Manual (Page 34)

34 AT45DQ321 [ADVANCE DATASHEET]
DS-45DQ321-031–DFLASH–12/2012
9.4.6 EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte
during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state.
The EPE bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or
program a protected region or a locked down sector or an attempt to erase or program a suspended sector. The EPE bit
is updated after every erase and program operation.
9.4.7 SLE Bit
The SLE bit indicates whether or not the Sector Lockdown command is enabled or disabled. If the SLE bit is a Logic 1,
then the Sector Lockdown command is still enabled and sectors can be locked down. If the SLE bit is a Logic 0, then the
Sector Lockdown command has been disabled and no further sectors can be locked down.
9.4.8 PS2 Bit
The PS2 bit indicates if a program operation has been suspended while using Buffer 2. If the PS2 bit is a Logic 1, then a
program operation has been suspended while Buffer 2 was being used, and any command attempts that would modify
the contents of Buffer 2 will be ignored.
9.4.9 PS1 Bit
The PS1 bit indicates if a program operation has been suspended while using Buffer 1. If the PS1 bit is a Logic 1, then a
program operation has been suspended while Buffer 1 was being used, and any command attempts that would modify
the contents of Buffer 1 will be ignored.
9.4.10 The ES bit
The ES bit indicates whether or not an erase has been suspended. If the ES bit is a Logic 1, then an erase operation
(page, block, sector, or chip) has been suspended.
9.5 Read Configuration Register
The non-volatile Configuration Register can be used to determine if the Quad-input Buffer 1 or 2 Write and Quad-output
Read Array commands have been enabled. Unlike the Status Register, the Configuration Register can only be read
when the device is in an idle state (when the RDY/ BUSY bit of the Status Register indicates that the device is in a ready
state).
To read the Configuration Register, the CS pin must first be asserted and the opcode of 3Fh must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting one byte of Configuration Register data on
the SO pin during subsequent clock cycles. The data being output will be a repeating byte as long as the CS pin remains
asserted and the clock pin is being pulsed.
At clock frequencies above f
CLK
, the first byte of data output will not be valid. Therefore, if operating at clock frequencies
above f
CLK
, at least two bytes of data must be clocked out from the device in order to determine the correct value of the
Configuration Register.
Deasserting the CS pin will terminate the Read Configuration Register operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
The Configuration Register is a non-volatile register; therefore, the contents of the Configuration Register are not
affected by power cycles or power-on reset operations.