Device operation, 1 dual-i/o and quad i/o operation – Rainbow Electronics AT45DQ321 User Manual
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AT45DQ321 [ADVANCE DATASHEET]
DS-45DQ321-031–DFLASH–12/2012
4.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated
opcodes are contained in
. A valid instruction starts with the falling
edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the
CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address
location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit
(MSB) first.
Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM
buffers. The three address bytes will be comprised of a number of dummy bits and a number of actual device address
bits, with the number of dummy bits varying depending on the operation being performed and the selected device page
size. Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using the
terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. The main
memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0, where PA12 - PA0 denotes the
13 address bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits required to designate
a byte address within the page. Therefore, when using the standard DataFlash page size, a total of 23 address bits are
used.
For the “power of 2” binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the
conventional terminology BFA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer.
Main memory addressing is referenced using the terminology A21 - A0, where A21 - A9 denotes the 13 address bits
required to designate a page address, and A8 - A0 denotes the 9 address bits required to designate a byte address
within a page. Therefore, when using the binary page size, a total of 22 address bits are used.
4.1
Dual-I/O and Quad I/O Operation
The AT45DQ321 features a Dual-input Buffer Write mode and a Dual-output Read mode that allows two bits of data to be
clocked into Buffer 1 or Buffer 2 or allows two bits of data to be read out of the device on every clock cycle to improve
throughputs. To accomplish this, both the SI and SO pins are utilized as inputs/outputs for the transfer of data bytes. With
the Dual-input Buffer Write command, the SO pin becomes an input along with the SI pin. Alternatively, with the Dual-
output Read Array command, the SI pin becomes an output along with the SO pin. For both Dual-I/O commands, the SO
pin will be referrred to as I/O
1
and the SI pin will be referred to as I/O
0
.
The device also supports a Quad-input Buffer Write mode and a Quad-output Read mode in which the WP and RESET
pins become data pins for even higher throughputs by allowing four bits of data to be clocked on every clock cycle into
one of the buffers or by allowing four bits of data to be read out of the device on every clock cycle. For the Quad-input
Buffer Write and Quad-output Read Array commands, the RESET, WP, SO and SI pins are referred to as I/O
3-0
where
RESET
becomes I/O
3
, WP becomes I/O
2
, SO becomes I/O
1
and SI becomes I/O
0
. The QE bit in the Configuration
Register must be set (via issuing the Quad Enable command) to enable the Quad-I/O operation and to enable the RESET
and WP pins to be converted to I/O data pins.