Teledyne LeCroy Protocol PCI Express Script Automation Test Tool User Manual
Page 37
Teledyne LeCroy
PCI Express Script Automation Test Tool User Manual
33
3.1.2.4.2 Test 1-2. TXN_BFT_CompletionTimeout
ASSERTIONS COVERED: TXN.8.0#1.1, TXN.8.0#2, TXN.8.0#3, TXN.8.0#4, TXN.8.0#5
Verify Basic Completion Timer requirements of a slotted Endpoint device. The Completion Timeout timer must not
expire in less than 50 µs, but it must expire if a Request is not completed in 50 ms.
Trainer Stimulus: trans_1-2_TXN_BFT_CompletionTimeout.peg
Recording Options: link_layer.rec
Verification Scripts: trans_1-2_TXN_BFT_CompletionTimeout.pevs
Test Algorithm:
1. Bring the link up.
2. Write 0x0000000F to Device Control Register, to enable Error Reporting for all error types.
3. Write 0xFFFFFFFF to Advanced Uncorrectable Error Status Register, to clear all prior error bits.
4. Write 0xFFFFFFFF to Advanced Correctable Error Status Register, to clear all prior error bits.
5. Main test stage. Do the following:
a. Wait for the DUT to initiate a Memory Read transaction (using MemRd32 TLP). Time out in four
seconds.
b. Wait for 49 microseconds.
c. Send the Memory Read Completion with Unsupported Request status.
d. Read the DUT Device Status Register and Advanced Uncorrectable Error Status Register.
e. Wait for the DUT to initiate another Memory Read transaction (using MemRd32 TLP). Time out
in four seconds.
f.
Wait for 50 milliseconds plus 1 microsecond.
g. Send the Memory Read Completion with Unsupported Request status.
6. Read Device Status Register.
7. Read Advanced Uncorrectable Error Status Register.
Pass/Fail Criteria:
Test should successfully progress though all test stages.
All test stages should be executed without protocol violations.
Verify that:
a) The following error conditions are set by the DUT in case the DUT has initiated the memory requests (if it did
not, no assertions can be checked, and the test is declared DONE):
• No errors are set in error registers in step 5d.
• The ERR_CORR bit is set in the Device Status register in step 6.
• The Completion Time-out bit is set in the Advanced Uncorrectable Error Status register (if implemented) in
step 7.