Teledyne LeCroy PCIBX64-X - Manual (Page 11)

9
RST# Reg [7..0]
71 f1 W
RST# Reg [15..8] 72 f2 W
RST# Reg [23, 20..16] 73 f3 W
Value 20..0 provides a delay time up to 5.368709 seconds in 2.56 microseconds increment.
D23 = 0, set the reset time to default of about 150 ms
D23 = 1, set the reset time to the value defined by D0 to D20
Reserved 74 f4
Reserved 75 f5
Read back 76 f6 R (D0=0, RST# asserted; D0=1, RST# de-asserted)
(D1=0, no 64 bit handshake detected; D1 = 1 64 operation
established) (PCIBX64 Only)
(D2=0, no 32 bit handshake detected; D2 = 1 32 operation
established) (PCIBX64 Only)
(D3=0, 33 MHz enabled slot; D3=1, 66 MHz enabled slot)
(D4=0, DUT not fully asserted; D4=1, DUT asserted)
32/64 status bit clear 77 f7 W 0x0 To clear status registers for 32 bit and 64 bit handshake.
Frequency Register 1 78 f8 R D[7..0]
Frequency Register 2 79 f9 R D[15..8]
Frequency Register 3 7a fa R D[23..16]
Measure Frequency 7b fb W Issue a write 0x0 to this address to start a conversion.
Then wait 15 ms and then read Frequency Registers
System Frequency, MHz = (D[23..0] * 100) / (1048575)
Ramp control, +5V 7c fc W D0 = 0, 50 us; D0 = 1, 10 ms