Serial data debug solutions 166 – Teledyne LeCroy Serial Data Debug Solutions User Manual
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Serial Data Debug Solutions
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919586 RevA
Scrambling on (if no TS2) - Some PCIEbus standards use a scrambling algorithm to reduce
electromagnetic interference (EMI) caused by repetitive data patterns. The LeCroy software automatically
detects if scrambling is being used by reading values in the TS2. If no TS2 exists in the transmission, you
can indicate its use by checking this box.
Level Type and Level in Percent - The message decoding algorithm setup is performed here. The level is
normally set up in %, and defaults to 50%. You can change the type from percent to. Adjust the level by
touching inside the number area to highlight the box title, and then use the oscilloscope front panel
Adjust knob to adjust. Or touch inside the number area twice and select a value using the pop-up numeric
keypad.
PLEASE NOTE THE FOLLOWING:
The set Level appears as a dotted horizontal line across the oscilloscope grid.
If initial decoding indicates that there are a number of error frames, make sure that the level is set to a
reasonable value.
PCIE-1X2 - Two Lanes, Each Either Upstream or Downstream
When selected, PCIE-1X2 shows Lane 0 up and Lane 0 down. The first 0 Lane is designated for Upstream packets
and the second 0 Lane is designated for Downstream. With this in mind, select a Source for Lane 0 up and Lane
0 down.
Now, as described previously, use the right-hand dialog to set Initial Bit Rate, Level Type, Level in Percent
(percent or absolute, based on type selection), and Scrambling on (if no TS2) checkbox for your PCIEbus D lane
information as desired.
PCIE-4X1 - Four Lanes All Upstream or All Downstream
When selected, PCIE-4X1 shows Lane 0 - 3. Select Sources for Lanes 0-3 all packets sent through these lanes are
either Upstream or Downstream.
Now, as described previously, use the right-hand dialog to set Initial Bit Rate, Level Type, Level in Percent
(percent or absolute, based on type selection), and Scrambling on (if no TS2) checkbox for your PCIEbus D lane
information as desired.