ADC ETU-751C - Manual (Page 22)

Functional Description 700-701-100-02
12 August 9, 2002 UTU-701 and ETU-751 List 1
G.703 Interface
The G.703 interface performs the following functions:
• provides a jumper-selectable 75 or 120
Ω
DTE interface (see “Installation and Startup” on page 23 for jumper
locations)
• allocates full or fractional portion of the total 2048 kbps bandwidth to and from the G.703 interface
• frames data according to G.704
• inserts an idle code into unused time slots at the G.703 output
• recovers timing from the received G.703 signal
• monitors multiframe CRC-4 errors in the received G.703 signal
• regenerates multiframe (CRC-4) code at the G.703 output
• regenerates time slot 0 at the G.703 output
• transports time slot 16 transparently between G.703 ports
The G.703 interface operates in the structured application mode when less than 32 time slots are selected and in
the unstructured mode when 32 time slots are selected (see
“System Configuration” on page 25 ). These modes are
described in detail in the “Rate Selectable Application Modes and Options” on page 14 .
HDSL Interface
The HDSL interface includes the HDSL framer, which performs HDSL multiplexing and demultiplexing;
a firmware-controlled programmable clock, which sets the HDSL line rate at the interface output; and the
transceiver and line-interface circuits for the single HDSL pair.
In the transmit direction, the HDSL framer accepts inputs from the G.703 data port as shown in Figure 5 . The data
is placed on the HDSL pair along with the HDSL overhead bits for presentation to the transceiver. A clock
representing the selected HDSL line rate is introduced to the transceiver, which outputs data on the single-pair
HDSL line. In the receive direction, overhead bits are stripped and processed, and time slots are output to the
G.703 interface.
Reversals of Tip and Ring wires are automatically detected and accommodated. The Monitor HDSL Span screen
indicates if the Tip and Ring wires are reversed.
System Timing Circuits
The UTU and ETU units can synchronize to any one of the following timing sources:
• G.703: Timing recovered from G.703 input signal
• EXT: External 2.048 MHz reference (available only for UTUs in a shelf with a management unit installed)
Processor
This device runs a program which in real-time:
• monitors the HDSL framer performance
• responds to user requests
• maintains a history of system performance