Agilent Technologies HDMP-3001 - Manual (Page 35)

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can result in from 0 to 8 mis-
matches (B3 bit errors). This
value can be inserted into the
Transmit Side G1 byte from bit
one to bit four as a Path REI.
The HDMP-3001 contains a 16-bit
B3 error counter that counts every
B3 bit error. When the perfor-
mance monitoring counters are
latched (LATCH_EVENT transi-
tions high), the value of this
counter is latched to the
B3ERRCNT[15:0] register, and the
B3 error counter is cleared.
3.9.4.9.5 Signal Label (C2) Monitoring
The received C2 bytes are moni-
tored so that reception of the
correct type of payload can be
verified. When a consistent C2
value is received for five consecu-
tive frames, the accepted value is
written to RX_C2[7:0]. The
RX_C2_D delta bit is set when a
new C2 value is accepted.
The expected value of the re-
ceived C2 bytes is provided in
EXP_C2[7:0]. If the current ac-
cepted value does not match the
expected value, and the accepted
value is NOT
• the all zeros Unequipped label,
• the 0x01(hex) Equipped -
non-specific label,
• 0xFC (hex), which in SONET
mode indicates non-VT-
structured STS-3c SPE with
Payload Defect(PDI-P), and in
SDH mode is reserved for
national use,
• 0xFF (hex), which is a
reserved label in SONET mode,
and in SDH mode indicates
VC-AIS,
then the Payload Label Mismatch
register bit, RX_PLM, is set high.
If the current accepted value is
the all zeros Unequipped label,
and the provided EXP_C2[7:0]
≠
0(hex), then the Unequipped reg-
ister bit, RX_UNEQ, is set high.
The RX_PLM and RX_UNEQ sig-
nals contribute to the insertion of
Path RDI on the Transmit Side G1
byte from bit 5 to bit 7(shown in
Table 1). When RX_PLM or
RX_UNEQ changes state, the
RX_PLM_D or the RX_UNEQ_D
delta bit is set.
3.9.4.9.6 Path REI Monitoring
Bits 1 through 4 (the four MSBs)
of the path status byte indicate
the number of B3 errors that were
detected by the remote terminal
in its received SPE/VC signal.
Only the binary values between 0
and 8 are legitimate. If a value
greater than 8 is received, it is in-
terpreted as zero errors (as is
specified in GR-253 and ITU-T
Recommendation G.707). The
HDMP-3001 contains a 16-bit G1
error counter that counts every
error indicated by G1 When the
performance monitoring counters
are latched (LATCH_EVENT tran-
sitions high), the value of this
counter is latched to the
G1_ERRCNT[15:0] register, and
the G1 error counter is cleared.
3.9.4.9.7 Path RDI Monitoring
The HDMP-3001 can be set to
monitor bit 5 of G1 (RDI-P indica-
tor), if RX_PRDI5 = 1; or bits 5, 6
and 7 of G1 (enhanced RDI-P indi-
cator), if RX_PRDI5 = 0.
Monitoring consists of checking
for G1_CONSEC[3:0] consecutive
received values of the monitored
bit(s) that are identical. When a
consistent value is received, bits
5, 6 and 7 of G1 are written to
RX_G1[2:0]. Accepted values are
compared to the previous con-
tents of this register. (All three
bits are written, but if RX_PRDI5
= 1, only G1 bit 5 and RX_G1[2]
are involved in the comparisons.)
When a new value is stored, the
RX_G1_D delta bit is set.
In SONET mode, an STS SPE de-
tects an RDI-P defect when an
RDI-P signal is received for five to
ten consecutive frames and termi-
nates the RDI-P defect when a
zero is in bits 5 and 6 of the G1
byte for five to ten consecutive
frames. It does not detect an RDI-
P defect and terminate the RDI-P
defect when it has detected an
AIS-P defect on the affected path.
3.9.4.9.8 Other POH Bytes
The remaining POH bytes are not
monitored by the HDMP-3001.
These include the path user chan-
nel (F2), the position indicator
(H4), the path growth/user chan-
nel (Z3/F3), the path growth/path
APS channel (Z4/K3), and the tan-
dem connection monitoring (Z5/
N1) bytes.
3.9.4.10 STS-3C/STM-1 Framer
The HDMP-3001 receive framer
operates in two modes. If
RX_FRMR_INH = 0 (the default),
the HDMP-3001 device framer is
enabled. In this mode, the parallel
input signal is not assumed to be
byte aligned. The SONET/SDH
framer locates the framing bytes
in the selected data signal to find
byte alignment and determine the
position of all TOH/SOH bytes.
After finding frame, the framer
shifts the data so that its output
data is byte aligned. It also de-
scrambles the data, performs B1
monitoring, and provides frame
counter outputs.
If RX_FRMR_INH = 1, the framer
circuitry in the HDMP-3001 is by-
passed. In this mode, the
HDMP-3001 requires a frame start
indication, RX_FRAME_IN, as
well as data and clock. The data
may come from a high-speed de-
vice that performs framing and
serial-to-parallel conversion of an
STS-3c/STM-1 signal or from a