Agilent Technologies HDMP-3001 - Manual (Page 5)

5
1. Introduction
The Agilent HDMP-3001 is a
highly integrated VLSI device that
provides mapping of Ethernet en-
capsulated packets into STS-3c
payloads. The HDMP-3001 sup-
ports full-duplex processing of
SONET/SDH data streams with
full section, line, and path over-
head processing. The device
supports framing pattern,
scrambling/descrambling, alarm
signal insertion/detection, and bit
interleaved parity (B1/B2/B3)
processing. Serial interfaces for
SONET/SDH TOH overhead bytes
are also provided. The HDMP-
3001 provides a line side interface
that operates at 155.52 Mb/s (8-bit
bus at 19.44 MHz). For Ethernet
applications a system interface
operating at 25 MHz is provided.
LAPS (Link Access Procedure –
SDH) support includes framing,
transparency processing, 32-bit
FCS processing, and self- synchro-
nous scrambling/descrambling
(X
43 +1). The HDMP-3001 also
provides GFP (Generic Framing
TOH OVERHEAD
INSERT
TX FRAMER
PARALLEL
INTERFACE
TO
LINE
8 BITS AT
19.44 MHz TO
TRANSCEIVER
8 BITS AT
19.44 MHz FROM
TRANSCEIVER
MICROPROCESSOR
INTERFACE
MDIO INTERFACE EEPROM INTERFACE
GPIO REGISTER
JTAG TEST
ACCESS PORT
TOH MONITOR POH MONITOR
RX FRAMER
TOH OVERHEAD
EXTRACT
SPE/VC
GENERATOR
PERFORMANCE
MONITOR
X 43 + 1
SCRAMBLER
LAPS/GFP
FRAME
PROCESSOR
LAPS/GFP
FRAME
PROCESSOR
X 43 + 1
DESCRAMBLER
POINTER
PROCESSOR
ETHERNET
MII
INTERFACE
TO
SYSTEM
TX FIFO
RX FIFO
E1, E2, F1 AND DCC
E1, E2, F1 AND DCC
8-BIT GENERIC
MICROPROCESSOR BUS
ETHERNET
MANAGEMENT BUS
STANDARD 2-WIRE
EEPROM BUS
4 BITS AT
25MHz
4 BITS AT
25MHz
TEST DATA 16 GENERAL
PURPOSE PINS
Procedure) support which in-
cludes framing, 32-bit FCS
processing, 16-bit HEC process-
ing, and self-synchronous
scrambling/descrambling
(X
43 +1).
1.1 Internal Functional Blocks
See the Figure 1 block diagram.
1.2 HDMP-3001 Features List
• Full Duplex Fast Ethernet
(100 Mb/s) over SDH/SONET
(OC-3c/STM-1).
• Handles the source and sink of
SONET/SDH section, line, and
path layers, with E1, E2, F1
and D1-D12 overhead inter-
faces in both transmit and
receive directions.
• Implements the processing of
STS-3c/STM-1 data streams
with full duplex mapping of
LAPS or GFP frames into
SONET/SDH payloads.
• Self-synchronous scrambler/
descrambler implementing
Figure 1. Functional Block Diagram
(X 43 +1) polynomial for LAPS/
GFP frames.
• Link-level scrambling function
to improve operational
robustness.
• Monitors link status when
mapping MAC frame into
SONET/SDH SPE. Statis-
tics of invalid frames are also
provided.
• Device control, configuration,
and status monitoring by
either an 8-bit external
microprocessor interface or an
MII management interface.
• Compliant with SONET/ SDH
specifications ANSI T1.105,
Bellcore GR-253-CORE and
ITU G.707.
• Provides IEEE 1149.1 JTAG
test port.
• Supports internal loopback
paths for diagnostics.
• Packaged in a 160 pin PQFP.
• Typical power dissipation
250 mW.