American Dynamics PMC-4U-CACI - Manual (Page 22)

Hardware and Software Design • Manufacturing Services
P a g e 22
Interrupts
PMC-4U interrupts are treated as auto-vectored. When the software
enters into an exception handler to deal with a PMC-4U interrupt the
software must read the interrupt register to determine the cause(s) of the
interrupt, change the interrupt mask, process accordingly to clear the
interrupt condition, and then clear the associated bit in the interrupt
register.
In order to clear the interrupt condition it will be necessary to access
registers in the UART or the SCC to determine the particular cause of the
interrupt, change the device interrupt enables, and service the device to
remove the cause of the interrupt. The SCC can be configured so that the
interrupt cause is read with an interrupt acknowledge/vector read cycle.
The interrupt level seen by the CPU is determined by the rest of the
system. The master interrupt can be disabled or enabled through the
PMC4U_BASE register. The individual enables for the four UART channels
and the SCC are controlled by the PMC4U_MSK register. In addition there
are registers in the UART and SCC that must be configured for the
particular conditions that are desired to generate an interrupt request.
An interrupt that is received from one of the UART channels or the SCC will
be latched into the PMC4U_IRUPT register. This interrupt will only affect
the interrupt status in the PMC4U_STAT register if the appropriate bit is
set in the PMC4U_MSK register. This in turn will only generate a host
interrupt only if the master interrupt enable is set in the PMC_BASE
register.
After the interrupt has been serviced and the interrupting condition no
longer exists the bit latched in the PMC4U_IRUPT register can be cleared
by writing a one to the respective bit. Then the mask bit can be set without
causing another interrupt.
The master enable is a mask that can be used to disable the interrupt from
reaching the CPU, but still leaves the internal interrupt request hardware
active which is useful for polled operation.
Power on initialization will provide a cleared interrupt request and interrupts
disabled.