American Dynamics PMC-4U-CACI - Manual (Page 8)

Hardware and Software Design • Manufacturing Services
P a g e 8
There is also a master interrupt enable that can be set to gate the
interrupt onto the PCI bus. The interrupt status is still available in a status
register even when the master interrupt enable is off. This facilitates polled
operation of interrupt conditions. The individual interrupt conditions are
specified in the internal registers of the UART and SCC. Please see the
XR16C854 and Z85C30 documentation for more information on interrupt
conditions and configuration.