Kontron VM62 - Manual (Page 17)

Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual
2.1 The 68EN360 (QUICC) on the VM62(A) / VM42(A)
Motorola’s MC68EN360 is a 32 bit high performance communication controller, combining powerful peripheral
functions with system integration functions and an on-chip microprocessor core (CPU32+).
On the VM62(A) / VM42(A), the on-chip CPU core is disabled and replaced with a more powerful external CPU, the
MC68040 or MC68060. The 68EN360 operates as a slave to the CPU in so-called ‘Companion Mode’. In this mode, the
68EN360 provides complete I/O functionality. The DMA channels can still obtain ownership of the CPU’s system bus
and therefore all on-chip DMA channels can address the whole of the address space. Moreover, important functions for
system integration, such as memory controller, clock generation, interrupt controller etc. are available in this mode,
meeting the requirements for the initialisation of the 68EN360, described later in this manual.
The programming of the 68EN360 begins by determining the block of on-chip RAM and registers via the MBAR
register. This register is located at a fixed address and can only be accessed in CPU space.
2.2 Address Decoder
2.2.1 Basic Structure
The address decoder of the VM62(A) / VM42(A) consists of two basic parts. A primary address decoder pre-decodes the
select signals for the processor data bus (in front of the bussizer) and for the I/O data bus (behind the bussizer). With
reference to initial boot cycles, the primary address decoder passes or enables a secondary address decoder stage. The
secondary address decoder stage is realised using the programmable chip slect logic of the MC68EN360. The 8 outputs of
the 68EN360 chip select logic are used for the base addresses of the various memory and I/O address ranges.
2.2.2 Boot Decoding
Due to the fact that the default boot memory used by the VM62(A) / VM42(A) is FLASH memory, which is completely
reprogrammable, a special boot decoder is provided. The boot memory is jumper selectable, the user having the choice
between FLASH (default), VMEbus memory or the on-board AutoBahn Interface. The boot decoder redirects the physical
address range 0H to 1000000H from either FLASH (DM60x), VMEbus or MP piggyback, providing the selected boot
memory is initially accessed.
Note
VMEbus boot memory must be located at VME base address 0H in Standard Supervisor Program/Data
address space.
Page 2-2 © 1995 PEP Modular Computers May 17, 1996