Kontron VM62 - Manual (Page 34)

VM62(A) / VM42(A) User’s Manual Chapter 2 Functional Description
2.6.8 Board Control/Status Register
Address: CS7 + $7 PEP Default Address $CD 00 00 07
Format: Byte
Access: read / write
Value after HW reset: 0
EN_BERR1 TR_WDG ACFAIL LED_G CS7 + $7
0 1 2 3 4 5 6 7
WDG EN_WDG BERR1 BERR2
Register Description
Name Value A c c e s s Description
WDG
bit 7 Read/Write Set by watchdog timer when timout has been reached. Used
to differentiate between resets caused by the watchdog and
resets caused by the reset button
(power up resets can be identified within the 68EN360)
BERR2
bit 6 Read/Write Set by VMEbus BUS monitor when timeout has been
reached. Used to identify BERR caused by this timer (see
also VMEbus Control/Status register)
BERR1
bit 5 Read/Write Set by on-board bus error timer when timeout has been
reached. Used to identify BERR caused by this timer
EN_WDG
bit 4 1 Read/Write Enable the watchdog timer. It can only be set once, and
remains enabled until the next reset
TR_WDG
bit 3 1 Read/Write Triggers the watchdog timer. Watchdog timeout = 512ms
EN_BERR1
bit 2 1 Read/Write Enables the on-board bus error timer. It also monitors all on-
board I/O cycles, including the time from the VMEbus
request to the VMEbus grant. Timeout = 8
µ
s
ACFAIL
bit 1 1 Read/Write VME ACFAIL signal latched when active in order to
distinguish a level 7 NMI from an ABORT or ACFAIL
LED_G
bit 0 1 Read/Write Enables the green ‘general purpose’ front panel LED
Note
Information may be lost if the user writes to bit 7.
May 17, 1996 © 1995 PEP Modular Computers Page 2-19