Kontron MSM800BEV - Manual (Page 58)

MSM800BEV / System Resources
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/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first MByte.
/SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor or DMA controller in
the system. When a microprocessor on the I/O channel wishes to drive /SMEMW, it must have the address lines
valid on the bus for one system clock period before driving /SMEMW active. Both signals are active low.
SYSCLK, output
This is an 8MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 66% duty cycle. This signal should only be used for synchronization.
TC, output
Terminal Count: provides a pulse when the terminal count for any DMA channel is reached. The TC completes a
DMA-Transfer. This signal is expected by the onboard floppy disk controller. Do not use this signal because it is
internally connected to the floppy controller.
/0WS, input
The Zero Wait State (/0WS) signal tells the microprocessor that it can complete the present bus cycle without
inserting any additional wait cycles. In order to run a memory cycle to a 16bit device without wait cycles, /0WS
is derived from an address decode gated with a Read or Write command. In order to run a memory cycle to an
8bit device with a minimum of one-wait states, /0WS should be driven active one system clock after the Read
or Write command is active, gated with the address decode for the device. Memory Read and Write commands
to an 8bit device are active on the falling edge of the system clock. /0WS is active low and should be driven
with an open collector or tri-state driver capable of sinking 20mA.
12V, +/- 5%
This signal is used only for the flat panel supply.
GROUND = 0V
This is used for the entire system.
VCC, +5V +/- 0.25V
This signal is used to supply other PC/104 peripheral cards. Maximum current is 2Amp.
7.1.2 PC104+ Bus
AD[31:00]
Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one or more data
cycles.
C/BE[3:0]*
Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined. During the
Data cycle, they define the byte enables.
PAR
Parity is even on AD[31:00] and C/BE[3:0]* and is required.
FRAME*
Frame is driven by the current master to indicate the start of a transaction and will remain active until the final
data cycle.
TRDY*
Target Ready indicates the selected device’s ability to complete the current data cycle of the traansaction.
Both IRDY* and TRDY* must be asserted to terminate a data cycle.
IRDY*
Initiator Ready indicates the master’s ability to complete the current data cycle of the transaction.
STOP*
Stop indicates the current selected device is requesting the master to stop the current transaction.