1 ide configuration registers, 2 ide bus master control registers – Compaq 4000N User Manual
Page 92
Chapter 5 Input/Output Interfaces
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
5-2
5.2.1.1
IDE Configuration Registers
The IDE interface is handled by the 82586 component and configured as a PCI device with bus
mastering capability. The PCI configuration registers for the IDE controller function (PCI device
#20, function #1) are listed in Table 5-1.
Table 5–1. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82586, Function 1)
PCI
Conf.
Addr.
Register
Value
on
Reset
PCI
Conf.
Addr.
Register
Value
on
Reset
00-01h
Vender ID
1106h
40h
Chip Enable reg.
02-03h
Device ID
0586h
41h
IDE Configuration
00h
04-05h
PCI Command
0000h
42h
Miscellaneous Control
06-07h
PCI Status
0000h
43h
FIFO Configuration
08h
Revision ID
0Ah
44h
Miscellaneous Control
09h
Programming
xxxxh
45h
Miscellaneous Control
0Ah
Sub-Class
01h
46h
Miscellaneous Control
C0h
0Bh
Base Class Code
01h
48h
Sec. IDE Drv.1 Timing Cntrl.
A8h
0Dh
Master Latency Timer
0000h
49h
Sec. IDE Drv.0 Timing Cntrl
A8h
0Eh
Header Type
80h
4Ah
Pri. IDE Drv.1 Timing Cntrl.
A8h
10-13h
Pri. Data/Cmd Base Addr.
1F0h
4Bh
Pri. IDE Drv.0 Timing Cntrl
A8h
14-17h
Pri. Cntrl./Sts. Base Addr.
3F4h
4Ch
Address Setup Time
18-1Bh
Sec. Data/Cmd Base Addr.
170h
4E, 4Fh
Non-1F0h Port Drive Timing
00FFh
1C-1Fh
Sec. Cntrl./Sts. Base Addr.
374h
50h
Sec. Drive 1 Ext. Timing
00h
20-23h
Bus Mstr. Cntrl. Reg. Base Addr.
51h
Sec. Drive 0 Ext. Timing
00h
24-27h
Mem. Base Addr. for MM I/O
52h
Pri. Drive 1 Ext. Timing
00h
3Ch
Interrupt Line
0Eh
53h
Pri. Drive 0 Ext. Timing
00h
3Dh
Interrupt Pin
54-5Fh
Reserved
3Eh
Min_GNT
60, 61h,
Sector Size for Pri. IDE
200h
3Fh
Min_LAT
68, 69h
Sector Size for Sec. IDE
200h
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2
IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the I/O mapped control registers
listed in Table 5-2.
Table 5–2. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
Size
(Bytes)
Register
Default
Value
00h
2
Bus Master IDE Command (Primary)
00h
02h
2
Bus Master IDE Status (Primary)
00h
04h
4
Bus Master IDE Descriptor Ptr (Pri.)
0000 0000h
08h
2
Bus Master IDE Command (Secondary)
00h
0Ah
2
Bus Master IDE Status (Secondary)
00h
0Ch
4
Bus Master IDE Descriptor Ptr (Sec.)
0000 0000h