ADLINK DAQe-2006 - Manual (Page 61)

Operation Theory 49
Timed Waveform Generation
This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.
The D/A output timing is provided through a combination of
counters in the FPGA on board. There are a total of five counters
to be specified. These counters include:
X UI_counter (24 bits): specify the DA Update Interval =
CHUI_counter/TIMEBASE
X UC_counter (24 bits): specify the total Update Counts in a
single waveform
X IC_counter (24 bits): specify the Iteration Counts of wave-
form
X DA_DLY1_counter (16 bits): specify the Delay from the trig-
ger to the first update start
X DA_DLY2_counter (16 bits): specify the Delay between two
consecutive waveform generations
Figure 4-14 shows a typical D/A timing diagram assuming the data
in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on
each rising edge of DAWR. The meaning of the counters enumer-
ated above are discussed in the following sections.