Echelon Neuron C - Manual (Page 188)

176 Memory Management
Using Neuron Chip Memory
The following section describes two different situations, using Neuron Chips or
Smart Transceivers with off-chip memory, and using Neuron Chips or Smart
Transceivers without off-chip memory.
Chips with Off-Chip Memory
On-chip memory for the Neuron 3150 Chip and FT 3150 Smart Transceiver
consists of RAM and EEPROM. On-chip memory for the Neuron 5000 Processor
and FT 5000 Smart Transceiver consists of RAM, but the memory map typically
contains ROM, EEPROM, and RAM areas (optionally also flash memory). For a
Series 5000 chip, the system firmware automatically synchronizes non-RAM
memory areas with the serial memory parts, as necessary.
Off-chip memory on these chips consists of one or more of ROM, RAM, EEPROM,
NVRAM, or flash memory regions. You specify the starting page number for each
region and the number of pages (a page is 256 bytes) when the device is defined.
If ROM is used, its starting address must be 0000. If ROM is not used, then flash
or NVRAM memory must take its place, starting at address 0000. The regions of
memory must be in the order shown in Figure 16. They need not be contiguous,
but they cannot overlap.
Memory mapped I/O devices can be connected to the Neuron 3150 Chip and FT
3150 Smart Transceiver. The devices should respond only to memory addresses
that correspond to any of the shaded areas in Figure 16.
Figure 16. Off-Chip Memory for the Neuron 3150 Chip, the FT 3150 Smart Transceiver, the
Neuron 5000 Processor, and the FT 5000 Smart Transceiver