Echelon Neuron C - Manual (Page 190)

178 Memory Management
Neuron firmware and can optionally (only on a Neuron 3150 Chip or FT
3150 Smart Transceiver) contain application code and constants. For a
Series 5000 chip, the ROM contains the system firmware image.
Off-chip ROM (only on a Neuron 3150 Chip or FT 3150 Smart
Transceiver) may be implemented with any non-volatile memory
technology, including ROM, PROM, EPROM, EEPROM, flash memory, or
non-volatile RAM. Off-chip ROM or any memory technology used in its
place must have a write-time delay of 0 (zero) ms if the memory is used to
include the Neuron firmware and start at address 0x0000. This
requirement prevents EEPROM from being used for storage of the
Neuron firmware. Off-chip EEPROM can be used for application code
and data storage.
• EEPROM : Non-volatile memory that can be changed during program
execution. Memory writes typically require 20 ms per byte for on-chip
EEPROM. EEPROM can contain application code, constants, and
EEPROM variables.
Off-chip EEPROM can be implemented with EEPROM, flash memory, or
non-volatile RAM. If you use flash memory you must configure the
NodeBuilder FX or Mini FX hardware template editor to indicate flash
memory. Memory writes to this area can cause the Neuron firmware to
delay. This delay allows the memory to complete the write. When
implemented with EEPROM, the delay for off-chip EEPROM writes is
configurable from 0 to 255 milliseconds using the NodeBuilder Hardware
Template Properties dialog. The delay for off-chip flash memory writes is
fixed at 10 ms for each 64- or 128-byte sector.
For Series 3100 devices, if flash is used for the EEPROM region, it can
also take the place of the ROM region. In this case, you cannot write to
the system area of the flash (see Memory Areas ), but you can write to the
user area. For more information, including the particular flash parts
supported, see
Use of Flash Memory on page 184.
EEPROM is not zeroed when the Neuron Chip or Smart Transceiver is
reset.
• RAM : Volatile memory that can be changed during program execution.
RAM can contain application code, constants, or variables.
The Neuron hardware does not implement wait states for slow devices.
The memory must be readable and writable in one machine cycle at the
selected system clock rate.
The off-chip RAM region can be used for code. Any portion of the off-chip
RAM used for code is retained over resets. The remainder of RAM, the
area not used for code, is zeroed each time the chip is reset.
Memory Areas
The Neuron firmware and the Neuron linker divide the memory regions into
memory areas as follows: