Altera MAX 10 Power - Manual (Page 17)

Entering or Exiting Sleep Mode
During power-up and configuration modes, the
sleep
signal must be low. When the
sleep
signal is
asserted, the device immediately enters sleep mode. Upon entering sleep mode, the functionality of the
device such as GCLK networks and I/O buffers are dynamically powered down—to minimize dynamic
power dissipation. All configuration data is retained when the device is in the sleep mode.
Entering Sleep Mode
The following figure shows the timing diagram when the device enters sleep mode.
Figure 3-3: Entering Sleep Mode Timing Diagram
clk
sleep
current_state
ioe
clk_ena[15:0]
sleep_status
Awake Entering Sleep
16’hFFFF Disabling 16’h0000
T1
T2
The following lists the sequence when the device enters sleep mode.
1. An internal or external request drives the
sleep
signal high, forcing the device to go into sleep mode.
2. After a delay of T1, the power management controller powers down all the I/O buffers by de-asserting
ioe
signal that connects to
oe
and
nsleep
ports of the I/O buffers.
3. After a delay of T2, the power management controller turns off all GCLK networks by disabling
clk_ena[15:0]
signal from LSB to MSB. After three clock cycles, the
clk_ena[15:0]
signal is fully
disabled and transits into the sleep state.
4. The power management controller remains in sleep state until the
sleep
signal is de-asserted.
5. User logic will latch the running counter value before entering the sleep state and output to
cnt_sleep_enter
port. The running counter is then frozen.
6.
gpio_pad_output
(GPIO) is tri-stated when
ioe
is de-asserted.
Exiting Sleep Mode
The following figure shows the timing diagram when the device exits sleep mode.
3-4 Entering or Exiting Sleep Mode
UG-M10PWR
2015.02.09
Altera Corporation Power Management Controller Reference Design
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