Altera Arria V GX FPGA - Manual (Page 27)

Chapter 6: Board Test System 6–5
Using the Board Test System
July 2012 Altera Corporation Arria V GX FPGA Development Kit
User Guide
■ PSO —Sets the MAX II PSO register. The following options are available:
■ Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
■ Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
■ PSR —Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1
for more information.
■ PSS —Displays the MAX II PSS register value. Refer to Table 6–1 for the list of
available options.
■ SRST —Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to Table 6–1 for more information.
1
Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST; or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Arria V GX Device 1, Arria V GX Device 2, and MAX II are always in the JTAG chain.
SW6 selects whether HSMA, HSMB, and FMC are in the chain. Set the SW6 switch in
the off position to include the interface in the JTAG chain. Refer to
Table 4–3 for
detailed settings.
1
If you plug in an external USB-Blaster cable to the JTAG header (J1), the On-Board
USB-Blaster II is disabled.
f For details on the JTAG chain, refer to the Arria V GX FPGA Development Board
Reference Manual. For USB-Blaster II configuration details, refer to the On-Board
USB-Blaster II page.
Page Select Override
(PSO)
Read / Write
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Page Select Switch
(PSS)
Read only
Holds the current value of the illuminated PGM LED (D12-
D14) based on the following encoding:
■ 0 = PGM LED (D14) and corresponds to the flash
memory page for the factory hardware design
■ 1 = PGM LED (D13) and corresponds to the flash
memory page for the user hardware 1 design
■ 2 = PGM LED (D12) and corresponds to the flash
memory page for the user hardware 2 design
Table 6–1. MAX II Registers (Part 2 of 2)
Register Name
Read/Write
Capability
Description