Altera Arria V GX FPGA - Manual (Page 39)

Chapter 6: Board Test System 6–17
Using the Board Test System
July 2012 Altera Corporation Arria V GX FPGA Development Kit
User Guide
Port
The Port control allows you to specify which interface to test. The following port tests
are available:
■ XCVR x4
■ CMOS x3
■ FMC XCVR x4
■ FMC CMOS x34
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■ Serial Loopback —Routes signals from the receiver to the transmitter. Enter the
following values to enable the serial loopbacks:
0 = high speed serial transceiver signals to loopback on the board
1 = serial loopback
2 = reverse serial loopback pre-CDR
4 = reverse serial loopback post-CDR
■ VOD —Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre —Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post —Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post —Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer —Specifies the setting for the receiver equalizer.
■ DC gain —Specifies the DC portion of the receiver equalizer.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS7 —Selects pseudo-random 7-bit sequences.
■ PRBS15 —Selects pseudo-random 15-bit sequences.
■ PRBS23 —Selects pseudo-random 23-bit sequences.
■ PRBS31 —Selects pseudo-random 31-bit sequences.
■ HF1 —highest frequency divide-by-2 data pattern "10101010"
■ HF2 —next highest frequency divide-by-6 data pattern "111000111000"
■ HF3 —second lowest frequency divide-by-22 data pattern
■ LF —lowest frequency divide by 33 data pattern